On Jan 5, 2008, at 1:18 AM, Bill Wendling <[EMAIL PROTECTED]> wrote:
> Author: void > Date: Sat Jan 5 03:18:04 2008 > New Revision: 45626 > > URL: http://llvm.org/viewvc/llvm-project?rev=45626&view=rev > Log: > Chris and Evan noticed that this check was compleatly fubared. I was > checking that there was a from a global instead of a load from the > stub > for a global, which is the one that's safe to hoist. > > Consider this program: > > volatile char G[100]; > int B(char *F, int N) { > for (; N > 0; --N) > F[N] = G[N]; > } > > In static mode, we shouldn't be hoisting the load from G: > > $ llc -relocation-model=static -o - a.bc -march=x86 -machine-licm > > LBB1_1: # bb.preheader > leal -1(%eax), %edx > testl %edx, %edx > movl $1, %edx > cmovns %eax, %edx > xorl %esi, %esi > LBB1_2: # bb > movb _G(%eax), %bl > movb %bl, (%ecx,%eax) > > > Modified: > llvm/trunk/lib/Target/X86/X86InstrInfo.cpp > > Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=45626&r1=45625&r2=45626&view=diff > > === > === > === > ===================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sat Jan 5 03:18:04 > 2008 > @@ -171,12 +171,15 @@ > case X86::MOV32rm: > if (MI->getOperand(1).isRegister()) { > unsigned Reg = MI->getOperand(1).getReg(); > + const X86Subtarget &ST = TM.getSubtarget<X86Subtarget>(); > > // Loads from global addresses which aren't redefined in the > function are > // side effect free. > if (Reg != 0 && I assume caller ensure this operant is side effect free? Can you change this to accept a list of operands which should be checked? For LICM, that means non-invariant operands. Also, please fix the comment. Thx, Evan > MRegisterInfo::isVirtualRegister(Reg) && > MI->getOperand(2).isImm() && MI->getOperand(3).isReg() && > - MI->getOperand(4).isGlobal() && MI->getOperand(2).getImm > () == 1 && > + MI->getOperand(4).isGlobal() && > + ST.GVRequiresExtraLoad(MI->getOperand(4).getGlobal(), TM, > false) && > + MI->getOperand(2).getImm() == 1 && > MI->getOperand(3).getReg() == 0) > return true; > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
