Author: lattner
Date: Sat Jan 5 23:55:01 2008
New Revision: 45653
URL: http://llvm.org/viewvc/llvm-project?rev=45653&view=rev
Log:
remove explicit isStore flags that are now inferrable.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=45653&r1=45652&r2=45653&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Sat Jan 5 23:55:01 2008
@@ -713,7 +713,7 @@
Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
[(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
}
-let isStore = 1, AddedComplexity = 10 in {
+let AddedComplexity = 10 in {
def PICSTR : AXI2<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
[(store GPR:$src, addrmodepc:$addr)]>;
@@ -878,7 +878,6 @@
} // isLoad
// Store
-let isStore = 1 in {
def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
"str", " $src, $addr",
[(store GPR:$src, addrmode2:$addr)]>;
@@ -893,6 +892,7 @@
[(truncstorei8 GPR:$src, addrmode2:$addr)]>;
// Store doubleword
+let isStore = 1 in
def STRD : AI3<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
"str", "d $src, $addr",
[]>, Requires<[IsARM, HasV5T]>;
@@ -933,7 +933,6 @@
"str", "b $src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb, (post_truncsti8 GPR:$src,
GPR:$base, am2offset:$offset))]>;
-} // isStore
//===----------------------------------------------------------------------===//
// Load / store multiple Instructions.
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=45653&r1=45652&r2=45653&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Sat Jan 5 23:55:01 2008
@@ -278,7 +278,6 @@
"ldr $dst, $addr", []>;
} // isLoad
-let isStore = 1 in {
def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr),
"str $src, $addr",
[(store GPR:$src, t_addrmode_s4:$addr)]>;
@@ -295,6 +294,7 @@
"str $src, $addr",
[(store GPR:$src, t_addrmode_sp:$addr)]>;
+let isStore = 1 in {
// Special instruction for spill. It cannot clobber condition register
// when it's expanded by eliminateCallFramePseudoInstr().
def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=45653&r1=45652&r2=45653&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Sat Jan 5 23:55:01 2008
@@ -98,7 +98,6 @@
[(set SPR:$dst, (load addrmode5:$addr))]>;
} // isLoad
-let isStore = 1 in {
def FSTD : ADI5<(outs), (ins DPR:$src, addrmode5:$addr),
"fstd", " $src, $addr",
[(store DPR:$src, addrmode5:$addr)]>;
@@ -106,7 +105,6 @@
def FSTS : ASI5<(outs), (ins SPR:$src, addrmode5:$addr),
"fsts", " $src, $addr",
[(store SPR:$src, addrmode5:$addr)]>;
-} // isStore
//===----------------------------------------------------------------------===//
// Load / store multiple Instructions.
_______________________________________________
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
