Re: [gem5-users] error: ... is not a member of Debug

[Robert PINSKER]

My experience was that:

DebugFlag("Tube")
Did not generate a file debug/Tube.hh

Whereas

DebugFlag("tube")
DID generate a file debug/tube.hh.

I am assuming that this is because the name of the corresponding file in the 
src tree was tube.hh not Tube.hh.
This is an assumption but I can't think of another reason.

Robert.

-Original Message-
From: Nilay Vaish [mailto:ni...@cs.wisc.edu] 
Sent: 03 October 2012 16:13
To: Robert PINSKER
Cc: gem5-users@gem5.org
Subject: Re: [gem5-users] error: ... is not a member of Debug

On Wed, 3 Oct 2012, Robert PINSKER wrote:

> Ah. I figured it out. For the benefit of anyone else reading this:
>
> If I use the directive DebugFlag('Tube') it doesn't generate anything because 
> my source file is tube.hh not Tube.hh.
>
> So I have to use DebugFlag('tube'). This means that the flag name I use in 
> the DPRINTF statement must also be "tube" not "Tube".
>

I think you are confusing two different things. As per my understanding,
DebugFlag('tube') will not make SCons look for a file tube.hh. SCons will 
generate the file "debug/tube.hh" which needs to included in the source file 
that uses the debug flag tube.hh. It really should not matter whether you name 
the file Tube.hh or tube.hh.

--
Nilay
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Re: [gem5-users] How to configure more than 1GB physical memory on ALPHA_FS

[Iordan Alexandru]

Never mind. I figured it out. I moved the newly compiled console binary to the 
binary folder of the full_system_image_files. Now it works!



 From: Iordan Alexandru 
To: gem5 users mailing list  
Sent: Wednesday, October 3, 2012 10:41 AM
Subject: Re: [gem5-users] How to configure more than 1GB physical memory on 
ALPHA_FS
 

After modifying the gem5/system/alpha/console/Makefile to point to the 
crosstool I donwloaded from gem5 website, I executed make all and recompiled 
the console. However, the following error occurred when I try to simulate:

$ ./build/ALPHA_FS/gem5.opt configs/example/fs.py -n 4 
--script=../fft_4c_atomic_large.rcs --caches --l2cache
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Oct  3 2012 10:24:38
gem5 started Oct  3 2012 10:35:21
gem5 executing on alexandru-laptop
command line: ./build/ALPHA_FS/gem5.opt configs/example/fs.py -n 4 
--script=../fft_4c_atomic_large.rcs --caches --l2cache
Global frequency set at 1 ticks per second
info: kernel located at: ../FullSystemImages/binaries/vmlinux
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
0: system.remote_gdb.listener: listening for remote gdb #2 on port 7002
0: system.remote_gdb.listener: listening for remote gdb #3 on port 7003
 REAL SIMULATION 
info: Entering event queue @ 0.  Starting simulation...
info: Launching CPU 1 @ 45273200
info: Launching CPU 2 @ 46404216
info: Launching CPU 3 @ 47534936
panic: M5 panic instruction called at pc = 0xfc31add0.
 @ cycle 70405376
[execute:build/ALPHA_FS/arch/alpha/atomic_simple_cpu_exec.cc, line 11243]
Memory Usage: 4329232 KBytes
Program aborted at cycle 70405376
Aborted


I set the mem size at 4 GB in Benchmarks.py. The highest value that does not 
cause this error is 2047 MB. Any ideas why this is happening?

Alexandru Iordan



 From: Ali Saidi 
To: gem5 users mailing list  
Sent: Tuesday, October 2, 2012 8:48 PM
Subject: Re: [gem5-users] How to configure more than 1GB physical memory on 
ALPHA_FS
 

You should just be able to compile it and use the compiled version instead of 
the one you downloaded from the website.
Ali
 
On 02.10.2012 13:44, Iordan Alexandru wrote:
Is it possible for you to give some more details on how to implemented what you 
said there? How should I update gem5/system/alpha/console/console.c so that I 
can use more than 2 GB of main memory in my simulations?
>
>Thanks in advance!
>
>Best regards,
>Alexandru Iordan 
>
>
>
>
>From:  Ali Saidi ; 
>To:  gem5 users mailing list ; 
>Subject:  Re: [gem5-users] How to configure more than 1GB physical memory on 
>ALPHA_FS 
>Sent:  Sun, Apr 22, 2012 11:29:23 AM 
> 
>
>You need to compile an updated version of the console binary in 
>the gem5/system/alpha/console directory. 
>Ail
>
>
>On Apr 18, 2012, at 4:56 PM, Seongil O wrote:
>
>Hi all, 
>>Could anyone inform me the way to configure more than 1GB physical memory on 
>>ALPHA_FS machine?
>>The ALPHA_FS works quite well when I configure 1GB memory on 
>>configs/common/Benchmarks.py.
>>However, when I modify the line 49 of Benchmark.py to "return '2GB'", my gem5 
>>aborts simulation during booting process with following error messages.
>>$ build/ALPHA_FS/gem5.fast configs/example/fs.py 
>>gem5 Simulator System.  http://gem5.org/
>>gem5 is copyrighted software; use the --copyright option for details.
>>gem5 compiled Mar 28 2012 22:37:29
>>gem5 started Apr 18 2012 16:50:01
>>gem5 executing on apollon
>>command line: build/ALPHA_FS/gem5.fast configs/example/fs.py
>>Global frequency set at 1 ticks per second
>>info: kernel located at: 
>>/cal/home/seongil/simulators/gem5/test/gem5-test/dist/alpha/binaries/vmlinux
>>Listening for system connection on port 3456
>>0: system.remote_gdb.listener: listening for remote gdb on port 7000
>> REAL SIMULATION 
>>info: Entering event queue @ 0.  Starting simulation...
>>warn: Prefetch instructions in Alpha do not do anything
>>panic: M5 panic instruction called at pc = 0xfc31add0.
>> @ cycle 470435551500
>>[execute:build/ALPHA_FS/arch/alpha/atomic_simple_cpu_exec.cc, line 11213]
>>Memory Usage: 2358804 KBytes
>>Program aborted at cycle 470435551500
>>Aborted
>> m5 slave terminal: Terminal 0 
>>M5 console: m5AlphaAccess @ 0xFD02
>>Got Configuration 623
>>memsize 8000 pages FFFC
>>First free page after ROM 0xFC018000
>>HWRPB 0xFC018000 l1pt 0xFC04 l2pt 0xFC042000 
>>l3pt_rpb 0xFC044000 l3pt_kernel 0xFC048000 l2reserv 
>>0xFC046000
>>kstart = 0xFC31, kend = 0xFC8964E0, kentry = 
>>0xFC31, numCPUs = 0x1
>>CPU Clock at 2000 MHz IntrClockFrequency=102

[gem5-users] Sharing L1 cache with two cpu

[Eliseu Miguel]

Hi, I want to sharing one L1 cache with two cpu o3. It is necessary
that each cpu have permission to access L1 in the way alternating at
positive and negative time of clock. Is it necessary the Ruby for make
it? Any idea for me? I am working alone and it is very dificult to
start. Thank you.

-- 
Eliseu César Miguel
Instituto de Ciências Exatas (ICEx)
Ciência da Computação
Universidade Federal de Alfenas
eli...@bcc.unifal-mg.edu.br

**  http://www.bcc.unifal-mg.edu.br/portal/?q=eliseu **
Na página você baixa de graça o livro: O terço do meio
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Re: [gem5-users] error: ... is not a member of Debug

[Nilay Vaish]

On Thu, 4 Oct 2012, Robert PINSKER wrote:


My experience was that:

DebugFlag("Tube")
Did not generate a file debug/Tube.hh

Whereas

DebugFlag("tube")
DID generate a file debug/tube.hh.

I am assuming that this is because the name of the corresponding file in the 
src tree was tube.hh not Tube.hh.
This is an assumption but I can't think of another reason.



I think you should carry out the entire experiment again. Make sure that 
you use the correct header file and that the debug flag is used some 
where.


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Re: [gem5-users] Network Message and Memory Message

[Nilay Vaish]

On Tue, 2 Oct 2012, tejasi pimpalkhute wrote:


Hi Tushar,

Thanks for looking into the code, I tried running the Network_test protocol
and got this error:

Global frequency set at 10 ticks per second
info: Entering event queue @ 0.  Starting simulation...
gem5.debug:
build/ALPHA_SE_Network_test/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc:78:
virtual void InputUnit_d::wakeup(): Assertion `m_vcs[vc]->get_state() ==
IDLE_' failed.
Program aborted at cycle 30
Aborted


I used this command to run the test-
./build/ALPHA_SE_Network_test/gem5.debug
configs/example/ruby_network_test.py --num-cpus=16 --num-dirs=16
--topology=Mesh --mesh-rows=4 --sim-cycles=1000 --injectionrate=0.01
--synthetic=0 --fixed-pkts --maxpackets=1000 --garnet-network=fixed


On a side note, I also wanted to ask you if Ruby_random_test and
Ruby_mem_test do inject any memory flits  in the network. Because, I tried
to dynamic cast the msgptr of these flits to MemoryMessage msgptr so that I
can extract the information about its memory address and type, but it
fails. Do you see any reason why it could be failing? I want to deal with
both network packets and off-chip memory packets in the network. Can you
please guide me which test will be appropriate for the same?



First, the Network test protocol does not access memory. Second, even 
other protocols do not send messages to the memory via the network that 
you are trying to modify. There are dedicated links between the 
directory controllers and the memory controllers.


The test to be used depends on what you want to test for.

--
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Re: [gem5-users] A possible bug when forwarding between stq and ldt

[Nilay Vaish]

On Mon, 1 Oct 2012, Veydan Wu wrote:


Hi, all,

I wonder if anyone encountered this before. I ran a SPEC2006 application
(GemsFDTD), there are two instructions 1: stq r24, 16(r30) followed by 2:
ldt f0, 16(r30), very close.

In the unmodified OOO execution, 1 forwards the value (0x17) to 2
correctly. If I separated them, and make 1 complete before 2 starts, then 2
has to read cache. Cache still returns the correct value (0x17), however,
in *AlphaISAInst::Ldt::completeAcc(...), getMem()* cannot return the
correct value, the reason is that it transforms the returned data (0x17) by
*(T*)data where T here is of type double.

In gdb, **(double*)* data return a value almost 0 while **data* gives the
correct value 0x17. Thus when **(T*)data* is provided to gtoh(...) in
getMem(...), 0 is returned.


You need to explain this better. It is not at all clear to me what you are 
trying to illustrate here.


--
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Re: [gem5-users] Adding a Cache Layer

[Nilay Vaish]

On Sun, 30 Sep 2012, Mann Mann wrote:


Hi All

I am working on GEM5 for my project.
objective is to explore various Cache Architectures on multiprocessor
systems.

My aim to add a Cache layer on MESI protocol, I have gone through GEM5
source number of times,
but couldnt identify where to start. I mean what files to be modified.



The protocol files are in src/mem/protocol directory.

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Re: [gem5-users] problem in running multiple SAME sepc2006 benchmarks under SE mode

[Tao Zhang]

Hi Nilay,

Maybe I didn't make it clear. What I want is to run Multi-programmed 
simulation rather than multi-threaded simulation. In other words, I want 
4 cores to run 4 benchmarks (though they are all same) and each core has 
only 1 thread. As a result, I set "np = 4 and numThreads = 1" in my 
configuration script. I also produced 4 identical LiveProcess() and 
assigned them to each core. However, the simulation immediately 
terminated after the cpu switching from atomic to detailed, with message 
"a thread reached the max instruction count". I go through the 
Simulation.py, src/cpu/base.cc, src/cpu/O3/commit_impl.cc but didn't 
find the clue that I have wrongly set the -F and -I with the same number 
(1).


If the instruction count is based on the thread and no change during the 
cpu switching, why I can use -F and -I together for single-core 
simulation? The final results show that the atomic cpu run the first 
1 instructions and then the detailed cpu run the second half 
instruction. The total "sim_insts" in the final stats is 20001. 
Also, I did a simple test to change the -F and -I number as "-F 1000 -I 
6000", which is supposed to work well. Unfortunately, I got the same 
result...


It should be easy to fix as soon as I can find the codes for the cpu 
switch. Do you mind tell me where it is so that I can work it out? Also, 
I have another question: Even though the benchmarks are same, I assume 
the physical address range to accommodate each benchmark is still 
different since gem5 generates 4 process stacks with different address 
mapping. Is it correct?


Thanks a lot!

Tao

On 10/03/2012 11:24 AM, Nilay Vaish wrote:

On Wed, 3 Oct 2012, Tao Zhang wrote:


Dear all,



I was trying to run multiple SAME spec2006 benchmarks under SE mode. For
example, I employed 4 cores and each core run bzip2 independently. 
When I

used fastforward "-F" and maximum instruction "-I", the whole simulation
terminated exactly after the CPU switching. It seems like the 
switched CPU
thought it has hit the maximum instruction number. Originally, I 
think it


What do you mean by seems like? Is it happening in a non-deterministic 
fashion? gem5 should have printed the reason for exiting the simulation.


may be caused by the use of the same binary file. However, after I 
read the
Simulation.py, both "-F" and "-I" are applied to the cpu models, 
rather than

the processes. Therefore, the switched CPU should start with instruction
number 0..



Instruction accounting is done on a per thread basis, so the 
simulation will end after switching of cpus as the threads still 
remain the same. I guess you know what you need to do to keep the 
simulation going after switching of cpus.


--
Nilay

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Re: [gem5-users] problem in running multiple SAME sepc2006 benchmarks under SE mode

[Nilay Vaish]

There are specific comments inline. Overall, I think you need to have a 
better understanding of the options that you are trying to work with.


On Thu, 4 Oct 2012, Tao Zhang wrote:


Hi Nilay,

Maybe I didn't make it clear. What I want is to run Multi-programmed 
simulation rather than multi-threaded simulation. In other words, I want 4 
cores to run 4 benchmarks (though they are all same) and each core has only 1 
thread. As a result, I set "np = 4 and numThreads = 1" in my configuration 
script. I also produced 4 identical LiveProcess() and assigned them to each 
core. However, the simulation immediately terminated after the cpu switching 
from atomic to detailed, with message "a thread reached the max instruction 
count". I go through the Simulation.py, src/cpu/base.cc, 
src/cpu/O3/commit_impl.cc but didn't find the clue that I have wrongly set 
the -F and -I with the same number (1).


Can you clearly state how is this different from what you expect?



If the instruction count is based on the thread and no change during the cpu 
switching, why I can use -F and -I together for single-core simulation? The


Why not? You need to better understand the meaning of those two options.

final results show that the atomic cpu run the first 1 instructions 
and then the detailed cpu run the second half instruction. The total 
"sim_insts" in the final stats is 20001. Also, I did a simple test to


What were the option values that you supplied?

change the -F and -I number as "-F 1000 -I 6000", which is supposed to work 
well. Unfortunately, I got the same result...


What's the same result that you are referring to?



It should be easy to fix as soon as I can find the codes for the cpu switch. 
Do you mind tell me where it is so that I can work it out? Also, I have


It is not clear what is incorrect, hence fixing some thing is not out of 
question right now.



another question: Even though the benchmarks are same, I assume the physical 
address range to accommodate each benchmark is still different since gem5 
generates 4 process stacks with different address mapping. Is it correct?




I think this is correct.

--
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Re: [gem5-users] problem in running multiple SAME sepc2006 benchmarks under SE mode

[Ali Saidi]

 

On 04.10.2012 11:43, Nilay Vaish wrote: 

> There are specific
comments inline. Overall, I think you need to have a 
> better
understanding of the options that you are trying to work with.
> 
> On
Thu, 4 Oct 2012, Tao Zhang wrote:
> 
>> Hi Nilay, Maybe I didn't make it
clear. What I want is to run Multi-programmed simulation rather than
multi-threaded simulation. In other words, I want 4 cores to run 4
benchmarks (though they are all same) and each core has only 1 thread.
As a result, I set "np = 4 and numThreads = 1" in my configuration
script. I also produced 4 identical LiveProcess() and assigned them to
each core. However, the simulation immediately terminated after the cpu
switching from atomic to detailed, with message "a thread reached the
max instruction count". I go through the Simulation.py, src/cpu/base.cc,
src/cpu/O3/commit_impl.cc but didn't find the clue that I have wrongly
set the -F and -I with the same number (1).
> 
> Can you clearly
state how is this different from what you expect?
> 
>> If the
instruction count is based on the thread and no change during the cpu
switching, why I can use -F and -I together for single-core simulation?
The
> 
> Why not? You need to better understand the meaning of those two
options.

It is not clear what is incorrect, hence fixing some thing is
not out of 
question right now.

The code is across two places. The CPUs
put exit events on their instruction queues
(http://grok.gem5.org/search?q=comInstEventQueue) and then the
simulation code handles what do do when the C++ portion of the code
exits (end the simulation, or restart with a different CPU; see
http://grok.gem5.org/xref/gem5/configs/common/Simulation.py#461).

>>
another question: Even though the benchmarks are same, I assume the
physical address range to accommodate each benchmark is still different
since gem5 generates 4 process stacks with different address mapping. Is
it correct?
> 
> I think this is correct.
> 
> --
> Nilay
>
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Re: [gem5-users] problem in running multiple SAME sepc2006 benchmarks under SE mode

[Tao Zhang]

Thank you very much , Ali. I will try to figure it out.

On 10/04/2012 12:48 PM, Ali Saidi wrote:


On 04.10.2012 11:43, Nilay Vaish wrote:


There are specific comments inline. Overall, I think you need to have a
better understanding of the options that you are trying to work with.

On Thu, 4 Oct 2012, Tao Zhang wrote:
Hi Nilay, Maybe I didn't make it clear. What I want is to run 
Multi-programmed simulation rather than multi-threaded simulation. 
In other words, I want 4 cores to run 4 benchmarks (though they are 
all same) and each core has only 1 thread. As a result, I set "np = 
4 and numThreads = 1" in my configuration script. I also produced 4 
identical LiveProcess() and assigned them to each core. However, the 
simulation immediately terminated after the cpu switching from 
atomic to detailed, with message "a thread reached the max 
instruction count". I go through the Simulation.py, src/cpu/base.cc, 
src/cpu/O3/commit_impl.cc but didn't find the clue that I have 
wrongly set the -F and -I with the same number (1).

Can you clearly state how is this different from what you expect?
If the instruction count is based on the thread and no change during 
the cpu switching, why I can use -F and -I together for single-core 
simulation? The

Why not? You need to better understand the meaning of those two options.
final results show that the atomic cpu run the first 1 
instructions and then the detailed cpu run the second half 
instruction. The total "sim_insts" in the final stats is 20001. 
Also, I did a simple test to

What were the option values that you supplied?
change the -F and -I number as "-F 1000 -I 6000", which is supposed 
to work well. Unfortunately, I got the same result...

What's the same result that you are referring to?
It should be easy to fix as soon as I can find the codes for the cpu 
switch. Do you mind tell me where it is so that I can work it out? 
Also, I have

It is not clear what is incorrect, hence fixing some thing is not out of
question right now.

The code is across two places. The CPUs put exit events on their instruction 
queues (http://grok.gem5.org/search?q=comInstEventQueue) and then the 
simulation code handles what do do when the C++ portion of the code exits (end 
the simulation, or restart with a different CPU; see 
http://grok.gem5.org/xref/gem5/configs/common/Simulation.py#461).


another question: Even though the benchmarks are same, I assume the 
physical address range to accommodate each benchmark is still 
different since gem5 generates 4 process stacks with different 
address mapping. Is it correct?

I think this is correct.

--
Nilay
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Re: [gem5-users] Network Message and Memory Message

[tejasi pimpalkhute]

Hi Nilay,

Thanks for throwing light on this. I want to arbitrate request packets
originated  the core (requiring off-chip memory access) at the router. Do
you think this is possible in Gem5?
My understanding was that both the memory request flits as well as network
flits are routed via interconnection networks. So, I modified the
SWallocator_d code. But now I am confused, if the memory request flits
don't travel through the GARNET network towards the main memory, what path
do the take to access main memory? I would really appreciate if you could
elaborate more on this. Thanks!

On Thu, Oct 4, 2012 at 9:46 AM, Nilay Vaish  wrote:

> On Tue, 2 Oct 2012, tejasi pimpalkhute wrote:
>
>  Hi Tushar,
>>
>> Thanks for looking into the code, I tried running the Network_test
>> protocol
>> and got this error:
>>
>> Global frequency set at 10 ticks per second
>> info: Entering event queue @ 0.  Starting simulation...
>> gem5.debug:
>> build/ALPHA_SE_Network_test/**mem/ruby/network/garnet/fixed-**
>> pipeline/InputUnit_d.cc:78:
>> virtual void InputUnit_d::wakeup(): Assertion `m_vcs[vc]->get_state() ==
>> IDLE_' failed.
>> Program aborted at cycle 30
>> Aborted
>>
>>
>> I used this command to run the test-
>> ./build/ALPHA_SE_Network_test/**gem5.debug
>> configs/example/ruby_network_**test.py --num-cpus=16 --num-dirs=16
>> --topology=Mesh --mesh-rows=4 --sim-cycles=1000 --injectionrate=0.01
>> --synthetic=0 --fixed-pkts --maxpackets=1000 --garnet-network=fixed
>>
>>
>> On a side note, I also wanted to ask you if Ruby_random_test and
>> Ruby_mem_test do inject any memory flits  in the network. Because, I tried
>> to dynamic cast the msgptr of these flits to MemoryMessage msgptr so that
>> I
>> can extract the information about its memory address and type, but it
>> fails. Do you see any reason why it could be failing? I want to deal with
>> both network packets and off-chip memory packets in the network. Can you
>> please guide me which test will be appropriate for the same?
>>
>>
> First, the Network test protocol does not access memory. Second, even
> other protocols do not send messages to the memory via the network that you
> are trying to modify. There are dedicated links between the directory
> controllers and the memory controllers.
>
> The test to be used depends on what you want to test for.
>
> --
> Nilay
>



-- 
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Re: [gem5-users] Questions on gem5 and SystemC, IP modeling, and architectural analysis.

[Rich Podraza]

Hi all,

I never got any responses on this, so instead I'll ask: is there a better forum 
or resource to find information and opinions on these questions? Seems like 
this mailing list is not the place.

Thanks,
Rich

From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On 
Behalf Of Rich Podraza
Sent: Tuesday, October 02, 2012 10:35 AM
To: gem5-users@gem5.org
Subject: [gem5-users] Questions on gem5 and SystemC, IP modeling, and 
architectural analysis.

I just reviewed the HiPEAC Computer Systems Week slides and videos posted on 
the tutorials page and I have some questions about gem5. I am doing system 
modeling with some other tools right now and am interested in how gem5 may or 
may not overlap with them. I think the tools look very promising but am unsure 
about the level of abstraction and seeming lack of cycle-accuracy.


1.   How does gem5 currently interact with or support SystemC models? I see 
lots of references to them being similar but not exactly that they are 
compatible.

2.   How much of the model library includes non-generic IPs? For example, 
an ARM PL341 instead of generic memory?

3.   For users who have extensive use of gem5 in architecture analysis, how 
much confidence do you have in comparing the simulation results from different 
configurations and relating that to real system architecture decisions? In 
other words, how well do the behavior changes in different configurations of 
generic models translate to different configurations of real IP?

Thanks for any comments!

Rich

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Re: [gem5-users] Questions on gem5 and SystemC, IP modeling, and architectural analysis.

[Steve Reinhardt]

Rich,

Sorry for the delay in responding.  Ali and I were comparing notes to come
up with a unified response.

We appreciate your interest in gem5.  We're very curious about what you are
looking for in a simulation tool, and what features or capabilities you see
are missing from other tools.  Even if gem5 doesn't meet your needs out of
the box, we'd be very interested in discussing with you whether and how we
might work to make gem5 something that does address your needs.  We're
always interested in increasing gem5's value, and it's typically the case
that by working together in an open-source framework like gem5 we can
leverage each other's investments to our mutual benefit.

> 1.   How does gem5 currently interact with or support SystemC models?
I see lots of references to them being similar but not exactly that they
are compatible.

You're correct that gem5 and SystemC are not currently compatible.  The
original M5 simulation environment (from which gem5 derives) began
development before SystemC TLM took off, but gem5 and TLM have roughly the
same goals in terms of supporting both "loosely timed" and "cycle
approximate" object-based modeling in a common environment, and as a result
have evolved some comparable (though distinct) internal interfaces.  Thus
we find it very useful for people who are familiar with SystemC TLM to use
that as a point of reference when explaining the goals of gem5.

Though we can't currently interoperate with SystemC models, this feature
has long been on our radar.  It's certainly very feasible. Some
universities and companies have connected SystemC models to the simulator
in the past and there are some papers about their experiences, although
none of them have contributed those interfaces back to the public code
base. Additionally, we have been converting the memory system within gem5
to use four-phase TLM2-like handshakes, which should make an adapter
straightforward to write.  We think it's just a matter of someone having
the motivation both to do the work and to contribute the code back.

> 2.   How much of the model library includes non-generic IPs? For
example, an ARM PL341 instead of generic memory?

There are some non-generic devices in the dev directory (PL111, PL031, and
other devices that are required for booting a system). Most gem5 users are
looking for larger trends where generic models that are suitably configured
are sufficient. The object-oriented nature of the simulator allows
different memory controllers or other devices to be plugged in.  Some
people in industry have developed models of their IPs, but these tend to be
more difficult to share so they don't show up in the public code base.

> 3.   For users who have extensive use of gem5 in architecture
analysis, how much confidence do you have in comparing the simulation
results from different configurations and relating that to real system
architecture decisions? In other words, how well do the behavior changes in
different configurations of generic models translate to different
configurations of real IP?

We've done some work on correlating gem5 performance results with real
systems.  Much of that has been internal to AMD and ARM so it's not
possible to say anything concrete.  One published work (from when Ali was a
grad student) is here: http://web.eecs.umich.edu/~stever/pubs/iosca05.pdf

Another correlation study was presented at a recent workshop:
Accuracy Evaluation of GEM5 Simulator System. A. Butko, R. Garibotti, L.
Ost, and G. Sassatelli. In the proceeding of the IEEE International
Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC),
York, United Kingdom, July 2012.
That paper doesn't seem to be easily accessible online, but the conclusion
states "According to the results, the accuracy varies from 1.39% to 17.94%
depending on the memory traffic. In the worst scenario, mismatch has been
shown to result from overly simple model of the external DDR memory in GEM5
that does not fairly model DRAM specifics."

Regards,

Steve & Ali


On Thu, Oct 4, 2012 at 11:21 AM, Rich Podraza  wrote:

>  Hi all,
>
> ** **
>
> I never got any responses on this, so instead I’ll ask: is there a better
> forum or resource to find information and opinions on these questions?
> Seems like this mailing list is not the place.
>
> ** **
>
> Thanks,
>
> Rich
>
> ** **
>
> *From:* gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] *On
> Behalf Of *Rich Podraza
> *Sent:* Tuesday, October 02, 2012 10:35 AM
> *To:* gem5-users@gem5.org
>
> *Subject:* [gem5-users] Questions on gem5 and SystemC, IP modeling, and
> architectural analysis.
>
>  ** **
>
> I just reviewed the HiPEAC Computer Systems Week slides and videos posted
> on the tutorials page and I have some questions about gem5. I am doing
> system modeling with some other tools right now and am interested in how
> gem5 may or may not overlap with them. I think the tools look very
> promising but am unsure about

Re: [gem5-users] Network Message and Memory Message

[Nilay Vaish]

On Thu, 4 Oct 2012, tejasi pimpalkhute wrote:


Hi Nilay,

Thanks for throwing light on this. I want to arbitrate request packets
originated  the core (requiring off-chip memory access) at the router. Do
you think this is possible in Gem5?
My understanding was that both the memory request flits as well as network
flits are routed via interconnection networks. So, I modified the
SWallocator_d code. But now I am confused, if the memory request flits
don't travel through the GARNET network towards the main memory, what path
do the take to access main memory? I would really appreciate if you could
elaborate more on this. Thanks!



In a typical case a core would generate load/store requests for the 
caches. The cache controllers and the directory controllers are connected 
using a network. So, if a controller is unable to handle some request, it 
forwards it to the next level controller. The forwarded message goes 
through the on-chip network. If a request reaches the directory 
controller, it forwards it to the memory controller. A Memory Msg (in 
gem5's terminology) is message from a directory controller to a memory 
controller or vice-versa. These message travel on dedicated links between 
directory controllers and memory controllers. These links are not part of 
Garnet.


--
Nilay
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Re: [gem5-users] Garnet-network regression?

[Marco Elver]

The problem was at my end, after trying different versions of
build-dependencies, swig was the problem. Swig versions 2.0.7 and 2.0.8
both break garnet; I am now using 2.0.4, which works. I would recommend
to anyone else having this issue to use an older version of swig.

-- Marco

On 28/09/12 23:19, Nilay Vaish wrote:
> On Fri, 28 Sep 2012, Marco Elver wrote:
>
>> Hi all,
>>
>> I am having a problem with a setup that used to work. The important flag
>> is --garnet-network, without which everything works just fine.
>>
>> Versions from before Sep 05 in the dev repo were working, unfortunately
>> I don't have the exact commit when it stopped working; if nobody has an
>> idea what is going wrong, I'll start bisecting.
>>
>> Does anyone have an idea where to start looking to fix it? (See attached
>> *.log files for gem5 output)
>>
>
> Likely that the problem is at your end. The following command line is
> works when I execute it on my machine --
>
> ./build/X86/gem5.debug ./configs/example/ruby_mem_test.py --functional
> 10 -l 4000 -n 16 --num-l2caches 16 --num-dirs 16 --topology Mesh
> --mesh-rows 4 --garnet-network=flexible
>
>
> I would suggest that you remove the build directory and recompile gem5.
>
> -- 
> Nilay
>


-- 
The University of Edinburgh is a charitable body, registered in
Scotland, with registration number SC005336.

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Re: [gem5-users] Network Message and Memory Message

[tejasi pimpalkhute]

Thanks a ton for explaining this, I think I was mistaken earlier. In that
case, can I know beforehand the physical address of the request flits which
will be going to the directory controller? Can I calculate the rank and
bank address of that flit as done in the memory controller (if the router
has information about the physical memory)? I could see some mapping
functions in the directory controller to map the address to the physical
address of memory. Can I use those to get final main memory address?
Sorry for bombarding you with questions , but I really need to understand
this well as I am implementing a memory-aware arbitration technique at the
router. I appreciate your patience.

On Thu, Oct 4, 2012 at 2:23 PM, Nilay Vaish  wrote:

> On Thu, 4 Oct 2012, tejasi pimpalkhute wrote:
>
>  Hi Nilay,
>>
>> Thanks for throwing light on this. I want to arbitrate request packets
>> originated  the core (requiring off-chip memory access) at the router. Do
>> you think this is possible in Gem5?
>> My understanding was that both the memory request flits as well as network
>> flits are routed via interconnection networks. So, I modified the
>> SWallocator_d code. But now I am confused, if the memory request flits
>> don't travel through the GARNET network towards the main memory, what path
>> do the take to access main memory? I would really appreciate if you could
>> elaborate more on this. Thanks!
>>
>>
> In a typical case a core would generate load/store requests for the
> caches. The cache controllers and the directory controllers are connected
> using a network. So, if a controller is unable to handle some request, it
> forwards it to the next level controller. The forwarded message goes
> through the on-chip network. If a request reaches the directory controller,
> it forwards it to the memory controller. A Memory Msg (in gem5's
> terminology) is message from a directory controller to a memory controller
> or vice-versa. These message travel on dedicated links between directory
> controllers and memory controllers. These links are not part of Garnet.
>
> --
> Nilay
>



-- 
Thanks and Regards,
Tejasi
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Re: [gem5-users] Network Message and Memory Message

[Nilay Vaish]

On Thu, 4 Oct 2012, tejasi pimpalkhute wrote:


Thanks a ton for explaining this, I think I was mistaken earlier. In that
case, can I know beforehand the physical address of the request flits which
will be going to the directory controller? Can I calculate the rank and


When router forwards a flit, it knows the final destination of the flit. 
So it should be possible to figure out if a flit is meant for the 
directory controller.



bank address of that flit as done in the memory controller (if the router
has information about the physical memory)? I could see some mapping
functions in the directory controller to map the address to the physical
address of memory. Can I use those to get final main memory address?


A flit holds pointer to a message that holds the physical address. You 
would need to read the memory controller code to figure out how to map the 
physical address to ranks and banks.


--
Nilay
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[gem5-users] questions about cache access in ruby

[Cookie]

Hi,

I have some questions about the cache access in Ruby. As shown in file
src/mem/protocol/MESI_CMP_directory-L1.sm:

in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank =
0) {
... ...
// *** DATA ACCESS ***
  Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
  if (is_valid(L1Dcache_entry)) {
// The tag matches for the L1, so the L1 ask the L2 for it
*trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,*
*L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);*
  } else {
... ...
if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
  // L1 does't have the line, but we have space for it in the
L1 let's see if the L2 has it
*  trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,*
*  L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);*
}
... ...
  }
}
---
1/ why the two triggered actions are the same? I've no idea when the
L1Dcache_entry is valid (which I think means there is the requested block
available in the L1D cache), why it still asks the L1 for it (as commented)
by triggering the same action as if the cache block is not in L1D? I think
it should be responded to the processor. Is it correct? If so, should the
action be "send data to requestor" or anything else? I am really confused
with the cache access part in Ruby, could you please give me any
instructions/explanations?

2/ the function is_valid(xxx) is called many times in the *.sm files. But
I've no idea where it is defined?

Thanks,
Yingying
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Re: [gem5-users] problem in running multiple SAME sepc2006 benchmarks under SE mode

[Tao Zhang]

Finally, I fixed the problem. This is a gem5's bug when using both "-I" 
and "-F" in a multi-core simulation under SE mode. Simply speaking, the 
problem is caused by 'stale' exit events scheduled by Atomic CPUs, which 
gem5 fails to delete before the cpu switching.


For example, if 4 cores are employed in the simulation and each core (no 
matter Atomic CPU or O3 CPU) has 1 thread (numThreads = 1). Then, each 
core will schedule a SimLoopExitEvent in its own comInstEventQueue (line 
146-152, src/cpu/base.cc). Once the event is detected, it's processed 
and an exit event is scheduled in mainEventQueue (line 57-60, 
src/sim/sim_events.cc). Since these four Atomic CPUs run the same 
benchmark, they hit the instruction number specified by "-F" in the same 
cycle. As a result, 4 SimLoopExitEvents are scheduled in mainEventQueue.


However, the mainEventQueue can only handle one exit event at one time 
(line 71, src/sim/simulate.cc). The first exit event can be correctly 
served and leave the rest 3 events in the mainEventQueue. The first exit 
event triggers the cpu switching and the system resumes without 
descheduling the other 3 exit events in the mainEventQueue (line 
456-458, configs/common/Simulation.py). As a consequence, the system 
immediately exits again and the whole simulation is terminated. 
(changeset 9217 has no "m5.doDrain()" for the cpu switching. Even the 
newest changeset adds this function, it still doesn't work).


This can explain why there is no problem in single-core simulation: only 
one exit event is scheduled by Atomic CPU. This MAY also indicate that 
multi-core with different benchmarks can work well, since only one local 
exit event is scheduled in the mainEventQueue. ("MAY" means this should 
be confirmed by gem5 maintainer).


Naively, I fixed the bug by using two global  variables "exitTick" and 
"exitTimesWithinOneCycle". The following code is added to 
src/sim/simulate.cc.

while (1)
{
...
if (exit_event != NULL)
{
if( exitTimesWithinOneCycle == 0 )
{
exitTick = curTick();
exitTimesWithinOneCycle++;
std::cout << "This is the " << exitTimesWithinOneCycle 
<< " exit events!" << std::endl;

}
else
if( exitTick == curTick() )
{
exitTimesWithinOneCycle++;
std::cout << "This is the " << 
exitTimesWithinOneCycle << " exit events!" << std::endl;

continue;
}
...
}
}

On 10/04/2012 12:43 PM, Nilay Vaish wrote:
There are specific comments inline. Overall, I think you need to have 
a better understanding of the options that you are trying to work with.


On Thu, 4 Oct 2012, Tao Zhang wrote:


Hi Nilay,

Maybe I didn't make it clear. What I want is to run Multi-programmed 
simulation rather than multi-threaded simulation. In other words, I 
want 4 cores to run 4 benchmarks (though they are all same) and each 
core has only 1 thread. As a result, I set "np = 4 and numThreads = 
1" in my configuration script. I also produced 4 identical 
LiveProcess() and assigned them to each core. However, the simulation 
immediately terminated after the cpu switching from atomic to 
detailed, with message "a thread reached the max instruction count". 
I go through the Simulation.py, src/cpu/base.cc, 
src/cpu/O3/commit_impl.cc but didn't find the clue that I have 
wrongly set the -F and -I with the same number (1).


Can you clearly state how is this different from what you expect?



If the instruction count is based on the thread and no change during 
the cpu switching, why I can use -F and -I together for single-core 
simulation? The


Why not? You need to better understand the meaning of those two options.

final results show that the atomic cpu run the first 1 
instructions and then the detailed cpu run the second half 
instruction. The total "sim_insts" in the final stats is 20001. 
Also, I did a simple test to


What were the option values that you supplied?

change the -F and -I number as "-F 1000 -I 6000", which is supposed 
to work well. Unfortunately, I got the same result...


What's the same result that you are referring to?



It should be easy to fix as soon as I can find the codes for the cpu 
switch. Do you mind tell me where it is so that I can work it out? 
Also, I have


It is not clear what is incorrect, hence fixing some thing is not out 
of question right now.



another question: Even though the benchmarks are same, I assume the 
physical address range to accommodate each benchmark is still 
different since gem5 generates 4 process stacks with different 
address mapping. Is it correct?




I think this is correct.

--
Nilay
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Re: [gem5-users] Problem with single stepping

[Tobias Friemel]

I have got some progress. It seems like the function "StaticInstPtr 
decode(ArmISA::PCState &nextPC)" is the only decode function that 
returns the right StaticInst. Things like setting the isMisc bit in the 
ExtMachInst seems to be crucial before decoding.


But I'm stuck with the next problem. Now, hopefully with the right 
StaticInst, I'm calling hasBranchTarget and the check for indirect 
controll passes. Then the default StaticInst::branchTarget function is 
called which panics with the message "StaticInst::branchTarget() called 
on instruction that is not an indirect branch." In comparison for a 
normal branch instruction (just b) the function B::branchTarget in 
arm/arch/generated/decoder.cc is called. I found a similar function for 
Bl, but not for Bx. Can it be that there is missing something?



Regards,
Tobias

Am 02.10.2012 22:19, schrieb Tobias Friemel:

Inst and si->machInst are both saying 12fff13.

Running with debug flag ExecAll prints bxeq. So I tried printing the 
machInst at 
http://grok.gem5.org/source/xref/gem5/src/cpu/exetrace.cc#108 and it's 
showing 1012FFF13. I'm not sure why there is a difference and if it's 
matters.



Regards,
Tobias

Am 02.10.2012 19:28, schrieb Ali Saidi:


Hi Tobias,

I still don't see how that instruction could be decoded as a teq. 
I've executed it a couple of times with text programs and it's always 
decoded as a bxeq in the Exec trace output.


Assuming you're instrumenting the code is setSingleStep) could you 
print out the inst and the si->machInst that are there? inst should 
be the same as what you've printed below and machInst has some bits 
pre-decoded that could be the problem, but I don't see how the 
simulator could be in a state where those are wrong.


Ali

On 02.10.2012 09:41, Tobias Friemel wrote:


From the objdump output it's "012fff13 bxeqr3".

And I used this code to get the instruction and print the decoded 
version:


MachInst inst;
FSTranslatingPortProxy &proxy = tc->getVirtProxy();
proxy.readBlob(pc.pc(), (uint8_t*)&inst, sizeof(MachInst));
StaticInstPtr si = tc->getDecoderPtr()->decode(inst, pc.pc());
DPRINTF(Fail, "Instr: %s\n", si->disassemble(pc.pc()).c_str());


Regards,
Tobias

Am 02.10.2012 16:34, schrieb Ali Saidi:


Hi Tobias,

I don't think it's possible that bxeq is a teqeq. The TEQ 
instruction doesn't write any destination registers including the 
PC, so I'm not sure how it could cause a branch.


Could you print out the bits of the machine instruction that you're 
having a problem with?


Thanks,

Ali

On 02.10.2012 09:19, Tobias Friemel wrote:

I have tested both versions, the stable and the development
branch. The problem with the "bxeq r3" instruction is that it
gets decoded to "teqeq   pc, r3, LSL pc" which seems to do the
same, but doesn't get marked as a control transfer instruction.
I'm still missing an idea for a workaround to this.

Regards,
Tobias



Am 20.09.2012 18:09, schrieb Ali Saidi:

The setSingleStep code isn't particularly robust, but you
should be able to address the issues that you've described
here. You can check if the instruction is a 32bit thumb
instruction by looking at the ExtMachInst and adjust it
appropriately. I don't know what version of the simulator
you're using, but we fixed some identification of branch
instructions recently. THat said I'm very surprised that
bxeq isn't recognized as it certainly should be.

Ali

On 20.09.2012 11:03, Tobias Friemel wrote:

Hello,
I'm working on a thesis that includes fault injection in connection 
with
gem5 (ARM specific) and I'm looking for a way to implement some 
sort of
single stepping for this. I already found the method the RemoteGDB 
uses,
but there seems to be a problem with some machine instructions.

What the RemoteGDB does, is looking at the current program counter 
and
setting a new breakpoint to the next PC. If the instruction at the
current PC is a branch, it also sets a new breakpoint to the branch
target. The first problem I found was that the bxeq instruction 
(like
the one that is in the example bootloader for arm) isn't recognized 
as a
branch instruction. Another problem is that for Thumb-2 
instructions,
the next PC is always set to 16 bit after the current, even if it's 
a 32
bit long instruction.

Maybe someone knows an easy way to fix this or if there is a better 
way
to get single stepping.


Regards,
Tobias
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[gem5-users] Problems with McPAT and gem5

[Ding, Hongyuan]

Dear All,
I'm new to gem5. Recently I tired to integrate McPAT on gem5. I found two 
possible tools:
1. m5-mcpat-parse-se.py, http://cseweb.ucsd.edu/~rstrong/
2. m5-mcpat.pl, https://www.cl.cam.ac.uk/~acr31/sicsa/

I tried a simple example in gem5 to get the output files:
build/ARM/gem5.opt configs/example/se.py -c 
tests/test-progs/hello/bin/arm/linux/hello

I used m5-mcpat-parse-se.py to transform the output files but got the following 
error information:
ERROR, UNEXPECTED EXCEPTION
int() argument must be a string or a number, not 'NoneType'
Traceback (most recent call last):
 File "m5-mcpat-parse-se.py", line 1896, in 
 exit_code = main()
 File "m5-mcpat-parse-se.py", line 1847, in main
 run()
 File "m5-mcpat-parse-se.py", line 1036, in run
 parseSystemConfig(config_file_path, stat_file_path, out_file_path, 
out_file_path_2, component_hash, stats_hash)
 File "m5-mcpat-parse-se.py", line 1682, in parseSystemConfig
 createComponentTree (cht, sht)
 File "m5-mcpat-parse-se.py", line 1568, in createComponentTree
 generateCalcStats(cht, sht)
 File "m5-mcpat-parse-se.py", line 1494, in generateCalcStats
 cht[options.system_name].statistics["total_cycles"] = 
str(int(sht["%s.sim_ticks"%(options.system_name)])/int(fastest_clock))
TypeError: int() argument must be a string or a number, not 'NoneType'

I used m5-mcpat.pl to get the xml file and used mcpat-exec.pl to run McPAT, but 
also got errors:
Parse error (couldn't find runtime_sec in XML file)

Then I used McPAT directly to run the XML file generated by m5-mcpat.pl, but 
got the following error information:
ERROR: no valid tag organizations found

I guess these two tools are too old to support the current version of gem5.
Does anyone has a modified tools for McPAT integration or some clues on how to 
fix it?
Thank you very much for any comments!

--
Best regards,
Hongyuan Ding
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Re: [gem5-users] Problem with single stepping

[Ali Saidi]

 

Hi Tobias, 

If memory serves, only direct control instructions have
branch targets because the target information is encoded in the
instruction. Indirect control targets don't because the instruction
itself is insufficient to provide a target; it requires reading a
register and branching to the address encoded in the register. B and Bl
are both direct control instructions while bx is indirect. 

Ali 

On
04.10.2012 22:25, Tobias Friemel wrote: 

> I have got some progress. It
seems like the function "StaticInstPtr decode(ArmISA::PCState &nextPC)"
is the only decode function that returns the right StaticInst. Things
like setting the isMisc bit in the ExtMachInst seems to be crucial
before decoding.
> 
> But I'm stuck with the next problem. Now,
hopefully with the right StaticInst, I'm calling hasBranchTarget and the
check for indirect controll passes. Then the default
StaticInst::branchTarget function is called which panics with the
message "StaticInst::branchTarget() called on instruction that is not an
indirect branch." In comparison for a normal branch instruction (just b)
the function B::branchTarget in arm/arch/generated/decoder.cc is called.
I found a similar function for Bl, but not for Bx. Can it be that there
is missing something?
> 
> Regards,
> Tobias
> 
> Am 02.10.2012 22:19,
schrieb Tobias Friemel: 
> 
>> Inst and si->machInst are both saying
12fff13. 
>> 
>> Running with debug flag ExecAll prints bxeq. So I tried
printing the machInst at
http://grok.gem5.org/source/xref/gem5/src/cpu/exetrace.cc#108 [2] and
it's showing 1012FFF13. I'm not sure why there is a difference and if
it's matters.
>> 
>> Regards,
>> Tobias
>> 
>> Am 02.10.2012 19:28,
schrieb Ali Saidi: 
>> 
>>> Hi Tobias, 
>>> 
>>> I still don't see how
that instruction could be decoded as a teq. I've executed it a couple of
times with text programs and it's always decoded as a bxeq in the Exec
trace output. 
>>> 
>>> Assuming you're instrumenting the code is
setSingleStep) could you print out the inst and the si->machInst that
are there? inst should be the same as what you've printed below and
machInst has some bits pre-decoded that could be the problem, but I
don't see how the simulator could be in a state where those are wrong.

>>> 
>>> Ali 
>>> 
>>> On 02.10.2012 09:41, Tobias Friemel wrote: 
>>>

 From the objdump output it's "012fff13 bxeq r3". 
 
 And I
used this code to get the instruction and print the decoded
version:
 
 MachInst inst;
 FSTranslatingPortProxy &proxy =
tc->getVirtProxy();
 proxy.readBlob(pc.pc(), (uint8_t*)&inst,
sizeof(MachInst));
 StaticInstPtr si =
tc->getDecoderPtr()->decode(inst, pc.pc());
 DPRINTF(Fail, "Instr:
%sn", si->disassemble(pc.pc()).c_str());
 
 Regards,

Tobias
 
 Am 02.10.2012 16:34, schrieb Ali Saidi: 
 
>
Hi Tobias, 
> 
> I don't think it's possible that bxeq is a
teqeq. The TEQ instruction doesn't write any destination registers
including the PC, so I'm not sure how it could cause a branch. 
>

> Could you print out the bits of the machine instruction that
you're having a problem with? 
> 
> Thanks, 
> 
> Ali

> 
> On 02.10.2012 09:19, Tobias Friemel wrote: 
> 
>>
I have tested both versions, the stable and the development branch. The
problem with the "bxeq r3" instruction is that it gets decoded to "teqeq
pc, r3, LSL pc" which seems to do the same, but doesn't get marked as a
control transfer instruction. I'm still missing an idea for a workaround
to this.
>> 
>> Regards,
>> Tobias
>> 
>> Am
20.09.2012 18:09, schrieb Ali Saidi: 
>> 
>>> The setSingleStep
code isn't particularly robust, but you should be able to address the
issues that you've described here. You can check if the instruction is a
32bit thumb instruction by looking at the ExtMachInst and adjust it
appropriately. I don't know what version of the simulator you're using,
but we fixed some identification of branch instructions recently. THat
said I'm very surprised that bxeq isn't recognized as it certainly
should be. 
>>> 
>>> Ali 
>>> 
>>> On 20.09.2012 11:03,
Tobias Friemel wrote: 
>>> 
 Hello,
 I'm working on
a thesis that includes fault injection in connection with 
 gem5
(ARM specific) and I'm looking for a way to implement some sort of

 single stepping for this. I already found the method the
RemoteGDB uses, 
 but there seems to be a problem with some
machine instructions.
 
 What the RemoteGDB does, is
looking at the current program counter and 
 setting a new
breakpoint to the next PC. If the instruction at the 
 current
PC is a branch, it also sets a new breakpoint to the branch 

target. The first problem I found was that the bxeq instruction (like

 the one that is in the example bootloader for arm) isn't
recognized as a 
 branch instruction. Another problem is