Re: [edk2-devel] [edk2-platforms][PATCH v5 5/6] Platform/Sgi: Define RD-V2 platform id values
Hi Prabin, Thank you for this patch. On Fri, Mar 1, 2024 at 08:30 AM, Prabin CA wrote: > > Add RD-V2 platform identification values including the part number > and configuration number. This information will be used in populating > the SMBIOS tables. In the cover letter you mention the following: The system architecture of the RD-V2 platform is similar to the RD-N2 platform, except for the CPU and L2 cache size. Unfortunately that information is lost when the patches are merged. I would prefer that to be included in the commit message for the relevant patch. Also, I cannot find a patch similar to 4/6 for RD-N2 and there is no clear information on how one can build the firmware for RD-N2 platform. Can you clarify, please? As you mention the differences from RD-N2 are CPU and L2 cache sizes, should the PPTT not be updated? I do not see a patch for that. Is something missing here? Regards, Sami Mujawar -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117254): https://edk2.groups.io/g/devel/message/117254 Mute This Topic: https://groups.io/mt/104668455/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms][PATCH v5 0/6] Platform/Sgi: Add support for RD-N2-Cfg3 and RD-V2 platform
Hi Prabin, To me the RD-V2 support appears to be incomplete (or the required information is not clear). Therefore, instead of stalling the entire series, I am going to drop patch 5/6 and 6/6 and merge the remaining patches. Please reply back to my queries for patch 5/6 and send a separate patch series for RD-V2. Regards, Sami Mujawar -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117255): https://edk2.groups.io/g/devel/message/117255 Mute This Topic: https://groups.io/mt/104668446/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms][PATCH v5 0/6] Platform/Sgi: Add support for RD-N2-Cfg3 and RD-V2 platform
Merged patches 1 to 4 as 7c26299112f3..344be33d497d. Thanks. Regards, Sami Mujawar -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117256): https://edk2.groups.io/g/devel/message/117256 Mute This Topic: https://groups.io/mt/104668446/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms][PATCH v5 4/9] Platform/Sgi: Introduce a flag to enable PCIe support for RD Platforms
Hi Prabin, Thank you for this patch. On Mon, Mar 11, 2024 at 06:14 AM, Prabin CA wrote: > > #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS = > \ > - ((14 + (FixedPcdGet32 (PcdChipCount) * 2)) + = > \ > + ((13 + (FixedPcdGet32 (PcdChipCount) * 2)) + = > \ > + (FeaturePcdGet (PcdPcieEnable)) + = > \ > (FixedPcdGet32 (PcdIoVirtSocExpBlkUartEnable) * = > \ > FixedPcdGet32 (PcdChipCount) * 2)) > =20 This is not correct FeaturePcdGet() returns a boolean value. Please update this code accordingly. Regards, Sami Mujawar -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117257): https://edk2.groups.io/g/devel/message/117257 Mute This Topic: https://groups.io/mt/104862630/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms][PATCH v5 7/9] Platform/Sgi: Extend SMBIOS support for RD-Fremont
Hi Prabin,
Thank you for this patch.
This patch does not cleanly apply on the latest edk2-platforms master
branch. Can you check, please?
Regards,
Sami Mujawar
On 11/03/2024 01:14 pm, Prabin CA wrote:
Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a
16 core platform with Poseidon CPU. Each of the CPUs include
64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache.
The platform also includes system level cache of 32MB and 8GB of RAM.
Signed-off-by: Prabin CA
---
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 5
+
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c| 5
-
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 5
-
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 1
+
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 6
++
5 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index 6fa39d407bc9..acfa45910aed 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -51,6 +51,10 @@
#define RD_V2_PART_NUM0x7F2
#define RD_V2_CONF_ID 0x1
+// RD-Fremont Platform Identification values
+#define RD_Fremont_PART_NUM 0x7EE
+#define RD_Fremont_CONF_ID0x1
+
#define SGI_CONFIG_MASK 0x0F
#define SGI_CONFIG_SHIFT 0x1C
#define SGI_PART_NUM_MASK 0xFFF
@@ -90,6 +94,7 @@ typedef enum {
RdN2Cfg1,
RdN2Cfg2,
RdV2,
+ RdFremont,
} ARM_RD_PRODUCT_ID;
// Arm ProductId look-up table
diff --git
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
index edf2a5f63c63..9c28b051ebc2 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
@@ -34,7 +34,8 @@
"RdN2\0" \
"RdN2Cfg1\0" \
"RdN2Cfg2\0" \
- "RdV2\0"
+ "RdV2\0" \
+ "RdFremont\0"
typedef enum {
ManufacturerName = 1,
@@ -74,6 +75,8 @@ STATIC GUID mSmbiosUid[] = {
{0xd2946d07, 0x8057, 0x4c26, {0xbf, 0x53, 0x78, 0xa6, 0x5b, 0xe1, 0xc1,
0x60}},
/* Rd-V2 */
{0x3b1180a3, 0x0744, 0x4194, {0xae, 0x2e, 0xed, 0xa5, 0xbc, 0x2e, 0x43,
0x45}},
+ /* Rd-Fremont*/
+ {0x904b28d6, 0x0662, 0x11ed, {0xb9, 0x39, 0x02, 0x42, 0xac, 0x12, 0x00,
0x02}},
};
/* System information */
diff --git
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
index ee269f707714..c39c1553f6aa 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
@@ -44,6 +44,7 @@
"Neoverse-N2\0" \
"Neoverse-N2\0" \
"Neoverse-V2\0" \
+ "Neoverse-Poseidon\0" \
"000-0\0" /* Serial number */ \
"783-3\0" \
"786-1\0" \
@@ -54,7 +55,8 @@
"7B7-1\0" \
"7B6-1\0" \
"7B7-1\0" \
- "7F2-1\0"
+ "7F2-1\0" \
+ "7EE-1\0"
typedef enum {
PartNumber = 1,
@@ -181,6 +183,7 @@ InstallType4ProcessorInformation (
case RdN2:
case RdN2Cfg1:
case RdV2:
+ case RdFremont:
mArmRdSmbiosType4.Base.CoreCount = CoreCount;
mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount;
mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
diff --git
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
index 4af72919a3f1..4cdea5b3b763 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
@@ -335,6 +335,7 @@ InstallType7CacheInformation (
mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
break;
case RdV2:
+ case RdFremont:
/* L1 instruction cache */
mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64;// 64KB
mArmRdSmbiosType7[0].Base.InstalledSize2 = 64;
Re: [edk2-devel] [edk2-platforms][PATCH v5 4/9] Platform/Sgi: Introduce a flag to enable PCIe support for RD Platforms
I am going to fix this locally before merging. With that, Reviewed-by: Sami Mujawar Regards, Sami Mujawar -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117259): https://edk2.groups.io/g/devel/message/117259 Mute This Topic: https://groups.io/mt/104862630/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms][PATCH v5 1/9] Platform/Sgi: Correct typo in defining CPPC performance limited register
Hi Prabin,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 11/03/2024 01:14 pm, Prabin CA wrote:
The reference design platform currently lacks the CPPC (Collaborative
Processor Performance Control) performance limited register as defined
by the ACPI 6.x specification. There is a typo in the macro definition
where the 'fastchannel address of the performance limited register' is
mentioned instead of the 'performance limited register address'.
Correcting this typo. However, it's important to retain the reference to
the performance limited register in the macro for future use, as it will
prove useful once functionalities such as power metering devices are
enabled.
Signed-off-by: Prabin CA
---
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index 033d398fdb63..3e24f569c95a 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -469,8 +469,7 @@ typedef struct {
@param [in] DesiredPerfReg Fastchannel address for desired performance
register.
-@param [in] PerfLimitedReg Fastchannel address for performance limited
-register.
+@param [in] PerfLimitedReg Address for performance limited register.
@param [in] GranularityMHz Granularity of the performance scale.
@param [in] HighestPerf Highest performance in linear scale.
@param [in] NominalPerf Nominal performance in linear scale.
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Re: [edk2-devel] [edk2-platforms][PATCH v5 2/9] Platform/Sgi: Update the datatype of PcdSmmuBase from u32 to u64
Hi Prabin, Thank you for this patch. Minor, EDKII does not have u32 and u64 types, otherwise these changes look good to me. I will reword the commit message before merging. Reviewed-by: Sami Mujawar Regards, Sami Mujawar On 11/03/2024 01:14 pm, Prabin CA wrote: From: Vivek Gautam On RD-N2 and previous generation platforms, the base address was within 32-bit region. However, on upcoming platforms, the SMMUv3 base address is beyond 32-bit address region. So, update the datatype of SMMUv3 base PCD. Signed-off-by: Prabin CA --- Platform/ARM/SgiPkg/SgiPlatform.dec | 2 +- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec index 103dff8471a7..4087ff6cad2e 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dec +++ b/Platform/ARM/SgiPkg/SgiPlatform.dec @@ -79,7 +79,7 @@ [PcdsFixedAtBuild] gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|0|UINT32|0x0014 # SMMU - gArmSgiTokenSpaceGuid.PcdSmmuBase|0|UINT32|0x001D + gArmSgiTokenSpaceGuid.PcdSmmuBase|0|UINT64|0x001D gArmSgiTokenSpaceGuid.PcdSmmuSize|0|UINT32|0x001E # GPIO Controller diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c index fa3cfbc730f6..62c212f3c5b0 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2018-2023, ARM Limited. All rights reserved. +* Copyright (c) 2018-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -167,8 +167,8 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; // Sub System Peripherals - SMMU - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet32 (PcdSmmuBase); - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet32 (PcdSmmuBase); + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdSmmuBase); + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdSmmuBase); VirtualMemoryTable[Index].Length = FixedPcdGet32 (PcdSmmuSize); VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117261): https://edk2.groups.io/g/devel/message/117261 Mute This Topic: https://groups.io/mt/104862627/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms][PATCH v5 3/9] Platform/Sgi: Refactor system memory base and size definitions
Hi Prabin, Thank you for this patch. These changes look good to me. Reviewed-by: Sami Mujawar Regards, Sami Mujawar On 11/03/2024 01:14 pm, Prabin CA wrote: In preparation of adding the next generation of reference design platform that have different memory map, refactor the PcdSystemMemoryBase and PcdSystemMemorySize PCD definitions from the common PCD definitions file into the various platform generation specific memory map PCD definitions file. Signed-off-by: Prabin CA --- Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc | 8 +++- Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 8 +++- Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 6 +- 3 files changed, 15 insertions(+), 7 deletions(-) diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc index 0c577c42..eab43b23ec6d 100644 --- a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc @@ -1,5 +1,5 @@ # -# Copyright (c) 2020 - 2022, Arm Limited. All rights reserved. +# Copyright (c) 2020 - 2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -67,3 +67,9 @@ [PcdsFixedAtBuild.common] gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x1C1D gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x0001 gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|136 + + # System Memory (1GB - 16MB of Trusted DRAM at the top of the + # 32bit address space) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F00 + diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc index de1d8ea24b89..35e27d42d5a2 100644 --- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc @@ -1,5 +1,5 @@ # -# Copyright (c) 2020 - 2023, Arm Limited. All rights reserved. +# Copyright (c) 2020 - 2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -75,3 +75,9 @@ [PcdsFixedAtBuild.common] # IO virtualization block gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base|0x108000 + + # System Memory (1GB - 16MB of Trusted DRAM at the top of the + # 32bit address space) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F00 + diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc index 26ecd9ed59a7..1cfe07c7e4ed 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc @@ -1,5 +1,5 @@ # -# Copyright (c) 2018 - 2022, ARM Limited. All rights reserved. +# Copyright (c) 2018 - 2024, Arm Limited. All rights reserved. # (C) Copyright 2021 Hewlett Packard Enterprise Development LP # # SPDX-License-Identifier: BSD-2-Clause-Patent @@ -131,10 +131,6 @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0 - # System Memory (1GB - 16MB of Trusted DRAM at the top of the 32bit address space) - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000 - gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F00 - # ACPI Table Version gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117262): https://edk2.groups.io/g/devel/message/117262 Mute This Topic: https://groups.io/mt/104862628/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms][PATCH v5 5/9] Platform/Sgi: Add ACPI tables for RD-Fremont platform
Hi Prabin,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 11/03/2024 01:14 pm, Prabin CA wrote:
From: Shriram K
RD-Fremont is the next platform in the Arm's reference design platform
series. This platform includes 32 CPUs but the fixed virtual platform
(FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in
the system and so the FVP simulates 16 clusters. In preparation for
adding support for this platform, add the initial set of ACPI tables and
reuse existing ACPI tables as applicable to boot a operating system on
this platform.
Signed-off-by: Prabin CA
---
Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf | 73
Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl | 196
Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc | 138 ++
Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc | 167 +
4 files changed, 574 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
new file mode 100644
index ..9d07001dec96
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
@@ -0,0 +1,73 @@
+## @file
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2024, Arm Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION= 0x0001001A
+ BASE_NAME = RdFremontAcpiTables
+ FILE_GUID = c712719a-0aaf-438c-9cdd-35ab4d60207d #
gArmSgiAcpiTablesGuid
+ MODULE_TYPE= USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dbg2.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ RdFremont/Dsdt.asl
+ RdFremont/Madt.aslc
+ RdFremont/Pptt.aslc
+ Spcr.aslc
+ SsdtEvents.asl
+ SsdtRos.asl
+ SsdtRosVirtioP9.asl
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/SgiPkg/SgiPlatform.dec
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmPlatformTokenSpaceGuid.PcdClusterCount
+
+ gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress
+ gArmSgiTokenSpaceGuid.PcdGpioController0Size
+ gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
+ gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
+ gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
+ gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioNetSize
+ gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt
+ gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioP9Size
+ gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt
+ gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv
+ gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
new file mode 100644
index ..8812ea877f7a
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
@@ -0,0 +1,196 @@
+/** @file
+* Differentiated System Description Table Fields (DSDT)
+*
+* Copyright (c) 2024, Arm Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.5, Chapter 5, Section 5.2.11.1, Differentiated System Description
+* Table (DSDT)
+*
+**/
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
+ EFI_ACPI_ARM_OEM_REVISION) {
+ Scope (_SB) {
+Device (CL00) { // Cluster 0
+ Name (_HID, "ACPI0010")
+ Name (_UID, 0)
+
+ Device (CP00) { // Neoverse Poseidon core 0
+Name (_HID, "ACPI0007")
+Name (_UID, 0)
+Name (_STA, 0xF)
+ }
+}
+
+Device (CL01) { // Cluster 1
+ Name (_HID, "ACPI0010")
+ Name (_UID, 1)
+
+ Device (CP01) { // Neoverse Poseidon core 1
+Name (_HID, "ACPI0007")
+Name (_UID, 1)
+Name (_STA, 0xF)
+
Re: [edk2-devel] [edk2-platforms][PATCH v5 6/9] Platform/Sgi: Add initial support for RD-Fremont platform
Hi Prabin, Thank you for this patch. These changes look good to me. Reviewed-by: Sami Mujawar Regards, Sami Mujawar On 11/03/2024 01:14 pm, Prabin CA wrote: The RD-Fremont fixed virtual platform simulates 16 CPUs and 8GB of RAM. Add initial support for this platform by adding the required platform build configuration files. This platform has considerable differences in its memory map compared to its predecessors. So add a corresponding memory map file as well to define the PCDs for its generation of platforms. Signed-off-by: Prabin CA --- Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc | 71 Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc | 55 +++ Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc | 10 +++ 3 files changed, 136 insertions(+) diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc b/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc new file mode 100644 index ..06c3b37388c1 --- /dev/null +++ b/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc @@ -0,0 +1,71 @@ +# +# Copyright (c) 2024, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[PcdsFixedAtBuild.common] + # System Peripherals + gArmSgiTokenSpaceGuid.PcdSmcCs0Base|0x0800 + gArmSgiTokenSpaceGuid.PcdSmcCs1Base|0x06 + gArmSgiTokenSpaceGuid.PcdSysPeriphBase|0x0C00 + gArmSgiTokenSpaceGuid.PcdSysPeriphSysRegBase|0x0C01 + + # SP804 dual timer + gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress|0x0C11 + gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize|0x0001 + gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt|216 + + # Virtio Disk + gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x0C13 + gArmSgiTokenSpaceGuid.PcdVirtioBlkSize|0x1 + gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt|184 + + # GPIO controller + gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x0C1D + gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x0001 + gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|168 + + # Ethernet + gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress|0x0C15 + gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt|186 + + # PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0C17 + + # Virtio P9 + gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress|0x0C19 + gArmSgiTokenSpaceGuid.PcdVirtioP9Size|0x1 + gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt|185 + + # PL370 - HDLCD1 + gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0EF6 + + # PL011 - Serial Debug UART + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x0EF7 + gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt|179 + + # PL011 - Serial Terminal + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|112 + + # System Memory (2GB - 128MB of Trusted DRAM at the top of the 32bit address space) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7800 + + # SMMU + gArmSgiTokenSpaceGuid.PcdSmmuBase|0x28000 + gArmSgiTokenSpaceGuid.PcdSmmuSize|0x400 + + # Non-Volatile variable storage + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x06 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x060140 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x060280 + + # Address bus width - 64TB address space + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip|46 + + # Timer & Watchdog interrupts + gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv|109 + gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv|108 + gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv|110 + gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|111 diff --git a/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc b/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc new file mode 100644 index ..b52d2f59e15d --- /dev/null +++ b/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc @@ -0,0 +1,55 @@ +# +# Copyright (c) 2024, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + + +# +# Defines Section - statements that will be processed to create a Makefile. +# + +[Defines] + PLATFORM_NAME = RdFremont + PLATFORM_GUID = fd140b0f-4467-4314-aa69-cd0bd712e08e + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001B + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES= AARCH64 + BUILD_TARGETS = NOOPT|DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/ARM/SgiPkg/SgiPlatform.fdf + BOARD_DXE_FV_COMPONENTS= Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc + BUILD_NUMBER = 1 + +# include common definitions from SgiPlatform.dsc +!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc +!include Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc + +# include common/basi
Re: [edk2-devel] [edk2-platforms][PATCH v5 8/9] Platform/Sgi: Low Power Idle States for RD-Fremont
Hi Prabin,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 11/03/2024 01:14 pm, Prabin CA wrote:
RD-Fremont platform supports two LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). The cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.
Signed-off-by: Prabin CA
---
Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl | 154
2 files changed, 155 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
index 9d07001dec96..7556c1239116 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
@@ -48,6 +48,7 @@ [FixedPcd]
gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+ gArmSgiTokenSpaceGuid.PcdOscLpiEnable
gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
index 8812ea877f7a..f921eeb2d99e 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
@@ -8,6 +8,9 @@
* @par Specification Reference:
* - ACPI 6.5, Chapter 5, Section 5.2.11.1, Differentiated System Description
* Table (DSDT)
+* - ACPI 6.5, Chapter 8, Section 8.4.3, Lower Power Idle States
+* - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section 3.1,
+* Idle management and Low Power Idle states
*
**/
@@ -17,6 +20,93 @@
DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
EFI_ACPI_ARM_OEM_REVISION) {
Scope (_SB) {
+/* _OSC: Operating System Capabilities */
+Method (_OSC, 4, Serialized) {
+ CreateDWordField (Arg3, 0x00, STS0)
+ CreateDWordField (Arg3, 0x04, CAP0)
+
+ /* Platform-wide Capabilities */
+ If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+/* OSC rev 1 supported, for other version, return failure */
+If (LEqual (Arg1, One)) {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+
+ If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+/* OS initiated LPI not supported */
+And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
+
+ If (And (CAP0, OSC_CAP_PLAT_COORDINATED_LPI)) {
+if (LEqual (FixedPcdGet32 (PcdOscLpiEnable), Zero)) {
+ And (CAP0, Not (OSC_CAP_PLAT_COORDINATED_LPI), CAP0)
+ Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+}
+ }
+} Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+}
+ } Else {
+And (STS0, Not (OSC_STS_MASK), STS0)
+Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+ }
+
+ Return (Arg3)
+}
+
+Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
+ 0, // Version
+ 0, // Level Index
+ 2, // Count
+ Package () {// WFI for CPU
+1,// Min residency (uS)
+1,// Wake latency (uS)
+1,// Flags
+0,// Arch Context lost Flags (no loss)
+0,// Residency Counter Frequency
+0,// No parent state
+ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+32, // Bit Width
+0,// Bit Offset
+0x, // Address
+3,// Access Size
+ )
+},
+ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI1-Core"
+ },
+ Package () {// Power Gating state for CPU
+150, // Min residency (uS)
+350, // Wake latency (uS)
+1,// Flags
+1,// Arch Context lost Flags (Core context lost)
+0,// Residency Counter Frequency
+0,// No parent state
+ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+32, // Bit Width
+0,
Re: [edk2-devel] [edk2-platforms][PATCH v5 9/9] Platform/Sgi: Add CPPC support for RD-Fremont platform
Hi Prabin,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 11/03/2024 01:14 pm, Prabin CA wrote:
Enable ACPI CPPC mechanism for RD-Fremont as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with LCP to set the
desired performance. In addition to this, RD-Fremont platform does not
support CPPC revision 1 and below. So update the _OSC method to let OSPM
know about this fact.
Signed-off-by: Prabin CA
---
Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl | 162
2 files changed, 163 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
index 7556c1239116..fcaa3299c4ea 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
@@ -48,6 +48,7 @@ [FixedPcd]
gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+ gArmSgiTokenSpaceGuid.PcdOscCppcEnable
gArmSgiTokenSpaceGuid.PcdOscLpiEnable
gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
index f921eeb2d99e..9c7266c79285 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
@@ -11,6 +11,10 @@
* - ACPI 6.5, Chapter 8, Section 8.4.3, Lower Power Idle States
* - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section
3.1,
* Idle management and Low Power Idle states
+* - ACPI 6.5, Chapter 8, Section 8.4.6, Collaborative Processor Performance
+* Control
+* - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section 3.2,
+* Performance management and Collaborative Processor Performance Control
*
**/
@@ -43,6 +47,20 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
}
}
+
+ If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) {
+/* CPPC revision 1 and below not supported */
+And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
+
+ If (And (CAP0, OSC_CAP_CPPC2_SUPPORT)) {
+if (LEqual (FixedPcdGet32 (PcdOscCppcEnable), Zero)) {
+ And (CAP0, Not (OSC_CAP_CPPC2_SUPPORT), CAP0)
+ Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+}
+ }
+
} Else {
And (STS0, Not (OSC_STS_MASK), STS0)
Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
@@ -116,6 +134,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_UID, 0)
Name (_STA, 0xF)
+Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x200093000, 0x0, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+ Package ()
+PSD_INIT (0)
+})
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -131,6 +158,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_UID, 1)
Name (_STA, 0xF)
+Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x200293000, 0x0, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+ Package ()
+PSD_INIT (1)
+})
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -146,6 +182,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_UID, 2)
Name (_STA, 0xF)
+Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x200493000, 0x0, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+ Package ()
+PSD_INIT (2)
+})
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -161,6 +206,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_UID, 3)
Name (_STA, 0xF)
+Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x200693000, 0x0, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+ Package ()
+PSD_INIT (3)
+})
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -176,6 +230,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_UID, 4)
Name (_STA, 0xF)
+Name (_CPC, Package()
+
Re: [edk2-devel] [edk2-platforms][PATCH v5 0/9] Platform/Sgi: Add support for RD-Fremont platform
Hi Prabin,
I am going to drop patch 7/9 that adds the SMBIOS support, and merge the
remaining series.
Please fix patch 7/9 and send it as a separate patch that adds SMBIOS
support for RD-Fremont.
Regards,
Sami Mujawar
On 11/03/2024 01:14 pm, Prabin CA wrote:
Changes since V4:
- Addressed the comments shared by Levi for V3.
Changes since V3:
- Rebase on top of latest upstream branch.
Changes since V2:
- Removed author's signed-off on the patches, which is owned by another author.
Changes since V1:
- Corrected memory map in the DSDT file.
This patch series introduce support for RD-Fremont reference design
platform. This platform includes 32 CPUs, but the fixed virtual platform
(FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in
the system and so the FVP simulates 16 clusters. Each of the CPUs
include 64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache.
The platform also includes system level cache of 32MB and 8GB of RAM.
Also, this patch series adding the extended SMBIO support for RD-Fremont
platform.
In addition to patches that introduce RD-Fremont platform, there are
four patches that update support for existing platforms. The first patch
in this series correct the typo while defining the CPPC support.
The second patch in this series changes the data type of PcdSmmuBase
from u32 to u64. The third patch refactor the system memory map base and
size values. The fourth patch add a flag to enable PCIE support for
existing and future platforms.
This patch series should be applied on top of the patch series
https://edk2.groups.io/g/devel/message/116262
Link to gitlab branch with the patches in this series -
https://gitlab.arm.com/infra-solutions/reference-design/platsw/edk2-platforms/-/commits/topics/rdfremont/
Prabin CA (7):
Platform/Sgi: Correct typo in defining CPPC performance limited register
Platform/Sgi: Refactor system memory base and size definitions
Platform/Sgi: Introduce a flag to enable PCIe support for RD Platforms
Platform/Sgi: Add initial support for RD-Fremont platform
Platform/Sgi: Extend SMBIOS support for RD-Fremont
Platform/Sgi: Low Power Idle States for RD-Fremont
Platform/Sgi: Add CPPC support for RD-Fremont platform
Shriram K (1):
Platform/Sgi: Add ACPI tables for RD-Fremont platform
Vivek Gautam (1):
Platform/Sgi: Update the datatype of PcdSmmuBase from u32 to u64
Platform/ARM/SgiPkg/SgiPlatform.dec |
3 +-
Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc |
8 +-
Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc |
8 +-
Platform/ARM/SgiPkg/{SgiMemoryMap2.dsc.inc => SgiMemoryMap3.dsc.inc} |
88 ++--
Platform/ARM/SgiPkg/SgiPlatform.dsc.inc |
12 +-
Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc |
4 +-
Platform/ARM/SgiPkg/{RdV1/RdV1.dsc => RdFremont/RdFremont.dsc}|
14 +-
Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc |
4 +-
Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc |
4 +-
Platform/ARM/SgiPkg/RdV1/RdV1.dsc |
4 +-
Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc |
4 +-
Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc |
4 +-
Platform/ARM/SgiPkg/SgiPlatform.fdf |
4 +-
Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf|
75 +++
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf |
5 +-
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h |
3 +-
Platform/ARM/SgiPkg/Include/SgiPlatform.h |
5 +
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c|
5 +-
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c |
5 +-
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c |
1 +
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c |
6 +
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c |
25 +-
Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl |
512
Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc|
138 ++
Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc|
167 +++
Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc |
10 +
26 files changed, 1033 insertions(+), 85 deletions(-)
copy Platform/ARM/SgiPkg/{SgiMemoryMap2.dsc.inc => SgiMemoryMap3.dsc.inc}
(62%)
copy Platform/ARM/SgiPkg/{RdV1/RdV1.dsc => RdFremont/RdFremont.dsc} (77%)
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
create mode 100644 Platform/ARM/SgiPkg/
Re: [edk2-devel] [edk2-platforms][PATCH v5 0/9] Platform/Sgi: Add support for RD-Fremont platform
Merged as 344be33d497d..b64443f7b8c3 Thanks. Regards, Sami Mujawar -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117268): https://edk2.groups.io/g/devel/message/117268 Mute This Topic: https://groups.io/mt/104862625/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
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*Reminder: Tools, CI, Code base construction meeting series* *When:* Monday, April 1, 2024 4:30pm to 5:30pm (UTC-07:00) America/Los Angeles *Where:* https://teams.microsoft.com/l/meetup-join/19%3ameeting_ZDI2ZDg4NmMtMjI1My00MzI5LWFmYjAtMGQyNjUzNTBjZGYw%40thread.v2/0?context=%7b%22Tid%22%3a%2272f988bf-86f1-41af-91ab-2d7cd011db47%22%2c%22Oid%22%3a%2223af6561-6e1c-450d-b917-d9d674eb3cb6%22%7d View Event ( https://edk2.groups.io/g/devel/viewevent?eventid=2159777 ) *Description:* TianoCore community, Microsoft and Intel will be hosting a series of open meetings to discuss build, CI, tools, and other related topics. If you are interested, have ideas/opinions please join us. These meetings will be Monday 4:30pm Pacific Time on Microsoft Teams. MS Teams Link in following discussion: * https://github.com/tianocore/edk2/discussions/2614 Anyone is welcome to join. * tianocore/edk2: EDK II (github.com) * tianocore/edk2-basetools: EDK II BaseTools Python tools as a PIP module (github.com) https://github.com/tianocore/edk2-basetools * tianocore/edk2-pytool-extensions: Extensions to the edk2 build system allowing for a more robust and plugin based build system and tool execution environment (github.com) https://github.com/tianocore/edk2-pytool-extensions * tianocore/edk2-pytool-library: Python library package that supports UEFI development (github.com) https://github.com/tianocore/edk2-pytool-library MS Teams Browser Clients * https://docs.microsoft.com/en-us/microsoftteams/get-clients?tabs=Windows#browser-client -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117269): https://edk2.groups.io/g/devel/message/117269 Mute This Topic: https://groups.io/mt/105255286/21656 Mute #cal-reminder:https://edk2.groups.io/g/devel/mutehashtag/cal-reminder Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH RESEND v1] MdePkg: Adds a PCD to define IPMI interface type
[AMD Official Use Only - General] Acked-by: Abner Chang > -Original Message- > From: Abdul Lateef Attar > Sent: Saturday, March 30, 2024 1:23 PM > To: devel@edk2.groups.io > Cc: Attar, AbdulLateef (Abdul Lateef) ; Chang, > Abner ; Michael D Kinney > ; Liming Gao ; > Zhiguang Liu > Subject: [PATCH RESEND v1] MdePkg: Adds a PCD to define IPMI interface > type > > Define IPMI interface type as per specification version 2.0, > section C1-1.1. > > Cc: Abner Chang > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Zhiguang Liu > Signed-off-by: Abdul Lateef Attar > --- > MdePkg/MdePkg.dec | 11 ++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec > index 0c18e1decd..396d960dca 100644 > --- a/MdePkg/MdePkg.dec > +++ b/MdePkg/MdePkg.dec > @@ -9,7 +9,7 @@ > # (C) Copyright 2016 - 2021 Hewlett Packard Enterprise Development LP > # Copyright (c) 2022, Loongson Technology Corporation Limited. All rights > reserved. > # Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. > -# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. > +# Copyright (C) 2023 - 2024, Advanced Micro Devices, Inc. All rights > reserved. > # Copyright (c) 2023, Ampere Computing LLC. All rights reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent > @@ -2401,6 +2401,15 @@ ># @Prompt Time-out for a response, internal > > gEfiMdePkgTokenSpaceGuid.PcdIpmiSsifResponseRetryIntervalMicrosecond| > 6|UINT32|0x0036 > > + ## Indicates IPMI Interface Type > + # The IPMI specification defines the following interface types: (section > C1- > 1.1) > + # 0 - Unknown > + # 1 - KCS : Keyboard Controller Style > + # 2 - SMIC: Server Management Interface Chip > + # 3 - BT : Block Transfer > + # 4 - SSIF: SMBus System Interface > + gEfiMdePkgTokenSpaceGuid.PcdIpmiInterfaceType|0|UINT8|0x0038 > + > [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AARCH64] >## GUID identifying the Rng algorithm implemented by CPU instruction. ># @Prompt CPU Rng algorithm's GUID. > -- > 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117270): https://edk2.groups.io/g/devel/message/117270 Mute This Topic: https://groups.io/mt/105228733/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-redfish-client][PATCH V5 1/2] RedfishClientPkg: Set SettingsObject URI as the config language
[AMD Official Use Only - General]
Hi Mike,
Just letting you know that I merged this patch set to clean up the backlogs. I
believe your comment was addressed in V5. Just let me know if you still find
any improper code.
Thanks
Abner
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Chang,
> Abner via groups.io
> Sent: Thursday, March 28, 2024 2:54 PM
> To: Nickle Wang ; devel@edk2.groups.io; Mike
> Maslenkin
> Cc: Igor Kulchytskyy
> Subject: Re: [edk2-devel] [edk2-redfish-client][PATCH V5 1/2]
> RedfishClientPkg: Set SettingsObject URI as the config language
>
> [AMD Official Use Only - General]
>
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> [AMD Official Use Only - General]
>
> Hi @Mike Maslenkin, would you like to review this patch again as I addressed
> your comments in V5 patch set.
> Thanks
> Abner
>
> > -Original Message-
> > From: Nickle Wang
> > Sent: Tuesday, March 26, 2024 8:14 PM
> > To: Chang, Abner ; devel@edk2.groups.io
> > Cc: Igor Kulchytskyy
> > Subject: RE: [edk2-redfish-client][PATCH V5 1/2] RedfishClientPkg: Set
> > SettingsObject URI as the config language
> >
> > Caution: This message originated from an External Source. Use proper
> caution
> > when opening attachments, clicking links, or responding.
> >
> >
> > Thanks for working on this, Abner.
> >
> >
> > Reviewed-by: Nickle Wang
> >
> > Regards,
> > Nickle
> >
> > > -Original Message-
> > > From: abner.ch...@amd.com
> > > Sent: Friday, March 22, 2024 10:41 PM
> > > To: devel@edk2.groups.io
> > > Cc: Igor Kulchytskyy ; Nickle Wang
>
> > > Subject: [edk2-redfish-client][PATCH V5 1/2] RedfishClientPkg: Set
> > SettingsObject
> > > URI as the config language
> > >
> > > External email: Use caution opening links or attachments
> > >
> > >
> > > From: Abner Chang
> > >
> > > Set SettingsObject URI in @Redfish.Settings resource as the config
> language
> > > which is the same as the config language of parent URI that mandates
> > > @Redfish.Settings.
> > > With this, we can find the config language of the properties in
> SettingsObject
> > URI.
> > >
> > > Signed-off-by: Abner Chang
> > > Cc: Igor Kulchytskyy
> > > Co-authored-by: Nickle Wang
> > > ---
> > > .../Library/RedfishFeatureUtilityLib.h| 17
> > > .../RedfishFeatureUtilityLib.c| 89 ---
> > > .../RedfishConfigLangMapDxe.c | 15 +++-
> > > 3 files changed, 104 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/RedfishClientPkg/Include/Library/RedfishFeatureUtilityLib.h
> > > b/RedfishClientPkg/Include/Library/RedfishFeatureUtilityLib.h
> > > index ba9ea01501..3c5f248eb7 100644
> > > --- a/RedfishClientPkg/Include/Library/RedfishFeatureUtilityLib.h
> > > +++ b/RedfishClientPkg/Include/Library/RedfishFeatureUtilityLib.h
> > > @@ -369,6 +369,23 @@ RedfishSetRedfishUri (
> > >INEFI_STRING Uri
> > >);
> > >
> > > +/**
> > > +
> > > + Save Redfish SettingsObject URI in database for further use.
> > > +
> > > + @param[in]ParentUri Parent URI of @Redfish.Settings
> > > property.
> > > + @param[in]SettingObjectUri Redfish SettingsObject Uri to save.
> > > +
> > > + @retval EFI_INVALID_PARAMETER SystemId is NULL or EMPTY
> > > + @retval EFI_SUCCESSRedfish uri is saved
> > > +
> > > +**/
> > > +EFI_STATUS
> > > +SetRedfishSettingsObjectsUri (
> > > + IN EFI_STRING ParentUri,
> > > + IN EFI_STRING SettingObjectUri
> > > + );
> > > +
> > > /**
> > >
> > >Get the property name by given Configure Language.
> > > diff --git
> > >
> a/RedfishClientPkg/Library/RedfishFeatureUtilityLib/RedfishFeatureUtilityLib.
> c
> > >
> b/RedfishClientPkg/Library/RedfishFeatureUtilityLib/RedfishFeatureUtilityLib.
> c
> > > index cc2b37b796..dda80c4608 100644
> > > ---
> > >
> a/RedfishClientPkg/Library/RedfishFeatureUtilityLib/RedfishFeatureUtilityLib.
> c
> > > +++
> b/RedfishClientPkg/Library/RedfishFeatureUtilityLib/RedfishFeatureUt
> > > +++ ilityLib.c
> > > @@ -2082,7 +2082,6 @@ GetConfigureLang (
> > >EFI_STRING ResultStr;
> > >EFI_STRING UnicodeUri;
> > >EFI_STATUS Status;
> > > - EFI_STRING StrFound;
> > >
> > >if (IS_EMPTY_STRING (Uri)) {
> > > return NULL;
> > > @@ -2101,18 +2100,6 @@ GetConfigureLang (
> > >}
> > >
> > >ConfigLang = RedfishGetConfigLanguage (UnicodeUri);
> > > - if (ConfigLang == NULL) {
> > > -//
> > > -// @Redfish.Settings share the same schema as its parent.
> > > -// Remove "Settings" and try again.
> > > -//
> > > -StrFound = StrStr (UnicodeUri, L"/Settings");
> > > -if (StrFound != NULL) {
> > > - StrFound[0] = L'\0';
> > > - DEBUG ((REDFISH_DEBUG_TRACE, "%a: \"Settings\" found in URI, try:
> > %s\n",
> > > __func__, UnicodeUri));
> > > - ConfigLang = RedfishGetConfigLanguage (UnicodeUri);
> > > -}
> > > - }
> > >
> > >Free
Re: [edk2-devel] [PATCH v2 0/3] CryptoPkg/BaseCryptLib: add additional RSAES-OAEP crypto functions
Appreciate your efforts in optimization of unit test, for this patch set: Looks good to me. Reviewed-by: Yi Li -Original Message- From: devel@edk2.groups.io On Behalf Of Chris Ruffin via groups.io Sent: Sunday, March 31, 2024 6:00 AM To: devel@edk2.groups.io Cc: Chris Ruffin Subject: [edk2-devel] [PATCH v2 0/3] CryptoPkg/BaseCryptLib: add additional RSAES-OAEP crypto functions From: Chris Ruffin v2 patchset adds: - Add digest length parameter to RsaOaepEncrypt(), RsaOaepDecrypt() so that SHA256, SHA384, SHA512 message digests and mask generation functions can be used with the API. - Add NullLib implementation for BaseCryptLibMbedTls - Cleanups from v1 review - Significantly refactored and expanded test suite: - Use UNIT_TEST_CONTEXT and abstaction to run same tests on Pkcs1v2Encrypt()/Pkcs1v2Decrypt() and RsaOaepEncrypt() RsaOaepDecrypt() - Align DER Certificate / PrivateKey used with Pkcs1v2 APIs with RsaN, RsaE, RsaD parameters used by RsaOaep APIs so that they represent the same keys. - Implement fixed ciphertext test for Pkcs1v2Decrypt(), RsaOaepDecrypt() - Implementation was also checked with wycheproof test vectors (not included in the patch). Chris Ruffin (3): CryptoPkg/BaseCryptLib: add additional RSAES-OAEP crypto functions CryptoPkg/Driver: add additional RSAES-OAEP crypto functions CryptoPkg/BaseCryptLibUnitTest: add unit test functions CryptoPkg/Driver/Crypto.c | 130 ++- CryptoPkg/Include/Library/BaseCryptLib.h | 117 +++ .../Pcd/PcdCryptoServiceFamilyEnable.h| 4 + .../Library/BaseCryptLib/Pk/CryptPkcs1Oaep.c | 598 -- .../BaseCryptLib/Pk/CryptPkcs1OaepNull.c | 130 ++- .../Pk/CryptPkcs1OaepNull.c | 135 +++- .../BaseCryptLibNull/Pk/CryptPkcs1OaepNull.c | 130 ++- .../BaseCryptLibOnProtocolPpi/CryptLib.c | 114 +++ CryptoPkg/Private/Protocol/Crypto.h | 109 ++- .../Library/BaseCryptLib/OaepEncryptTests.c | 758 -- 10 files changed, 2098 insertions(+), 127 deletions(-) -- 2.44.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117272): https://edk2.groups.io/g/devel/message/117272 Mute This Topic: https://groups.io/mt/105239222/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2 1/1] MdeModulePkg/AcpiTableDxe: PCD switch to avoid using ACPI reclaim memory
Reviewed-by: Zhiguang Liu
> -Original Message-
> From: Li, Aaron
> Sent: Tuesday, March 26, 2024 3:58 PM
> To: devel@edk2.groups.io
> Cc: Liu, Zhiguang ; Bi, Dandan
> ; Liming Gao ; Liu, Yun Y
> ; Yao, Jiewen ; Ni, Ray
> ; Kinney, Michael D
> Subject: [PATCH v2 1/1] MdeModulePkg/AcpiTableDxe: PCD switch to avoid
> using ACPI reclaim memory
>
> UEFI spec defined ACPI Tables at boot time can be contained in memory of
> type EfiACPIReclaimMemory or EfiAcpiMemoryNVS, although InstallAcpiTable
> with AcpiTableProtocol will only allocate memory with type
> EfiACPIReclaimMemory (Except FACS).
>
> This patch provides an optional method controlled by PCD to avoid using
> EfiACPIReclaimMemory, by setting the PCD PcdNoACPIReclaimMemory to
> TRUE, all ACPI allocated memory will use EfiAcpiMemoryNVS instead.
>
> Cc: Zhiguang Liu
> Cc: Dandan Bi
> Cc: Liming Gao
> Cc: Liu Yun
> Cc: Jiewen Yao
> Cc: Ray Ni
> Cc: Michael D Kinney
> Signed-off-by: Aaron Li
> ---
> MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 37
> +++-
> MdeModulePkg/MdeModulePkg.dec| 7
> MdeModulePkg/MdeModulePkg.uni| 8 +
> MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf| 1 +
> 4 files changed, 45 insertions(+), 8 deletions(-)
>
> diff --git a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
> b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
> index e09bc9b704f5..080768033cfa 100644
> --- a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
> +++ b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
> @@ -340,6 +340,7 @@ ReallocateAcpiTableBuffer (
>EFI_ACPI_TABLE_INSTANCE TempPrivateData;
>EFI_STATUS Status;
>UINT64 CurrentData;
> + EFI_MEMORY_TYPE AcpiAllocateMemoryType;
>
>CopyMem (&TempPrivateData, AcpiTableInstance, sizeof
> (EFI_ACPI_TABLE_INSTANCE));
>//
> @@ -359,6 +360,12 @@ ReallocateAcpiTableBuffer (
> NewMaxTableNumber * sizeof (UINT32);
>}
>
> + if (PcdGetBool (PcdNoACPIReclaimMemory)) {
> +AcpiAllocateMemoryType = EfiACPIMemoryNVS; } else {
> +AcpiAllocateMemoryType = EfiACPIReclaimMemory; }
> +
>if (mAcpiTableAllocType != AllocateAnyPages) {
> //
> // Allocate memory in the lower 32 bit of address range for @@ -372,13
> +379,13 @@ ReallocateAcpiTableBuffer (
> PageAddress = 0x;
> Status = gBS->AllocatePages (
> mAcpiTableAllocType,
> - EfiACPIReclaimMemory,
> + AcpiAllocateMemoryType,
> EFI_SIZE_TO_PAGES (TotalSize),
> &PageAddress
> );
>} else {
> Status = gBS->AllocatePool (
> -EfiACPIReclaimMemory,
> +AcpiAllocateMemoryType,
> TotalSize,
> (VOID **)&Pointer
> );
> @@ -512,6 +519,7 @@ AddTableToList (
>EFI_PHYSICAL_ADDRESS AllocPhysAddress;
>UINT64Buffer64;
>BOOLEAN AddToRsdt;
> + EFI_MEMORY_TYPE AcpiAllocateMemoryType;
>
>//
>// Check for invalid input parameters @@ -550,6 +558,12 @@
> AddTableToList (
>CurrentTableList->TableSize = CurrentTableSize;
>CurrentTableList->PoolAllocation = FALSE;
>
> + if (PcdGetBool (PcdNoACPIReclaimMemory)) {
> +AcpiAllocateMemoryType = EfiACPIMemoryNVS; } else {
> +AcpiAllocateMemoryType = EfiACPIReclaimMemory; }
> +
>//
>// Allocation memory type depends on the type of the table
>//
> @@ -585,7 +599,7 @@ AddTableToList (
> // such as AArch64 that allocate multiples of 64 KB
> //
> Status = gBS->AllocatePool (
> -EfiACPIReclaimMemory,
> +AcpiAllocateMemoryType,
> CurrentTableList->TableSize,
> (VOID **)&CurrentTableList->Table
> );
> @@ -596,7 +610,7 @@ AddTableToList (
> //
> Status = gBS->AllocatePages (
> mAcpiTableAllocType,
> -EfiACPIReclaimMemory,
> +AcpiAllocateMemoryType,
> EFI_SIZE_TO_PAGES (CurrentTableList->TableSize),
> &AllocPhysAddress
> );
> @@ -1944,6 +1958,7 @@ AcpiTableAcpiTableConstructor (
>UINTN RsdpTableSize;
>UINT8 *Pointer;
>EFI_PHYSICAL_ADDRESS PageAddress;
> + EFI_MEMORY_TYPE AcpiAllocateMemoryType;
>
>//
>// Check for invalid input parameters @@ -1978,17 +1993,23 @@
> AcpiTableAcpiTableConstructor (
> RsdpTableSize += sizeof
> (EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER);
>}
>
> + if (PcdGetBool (PcdNoACPIReclaimMemory)) {
> +AcpiAllocateMemoryType = EfiACPIMemoryNVS; } else
Re: [edk2-devel] [PATCH v2 1/1] MdeModulePkg/AcpiTableDxe: PCD switch to avoid using ACPI reclaim memory
Hi Liming,
Could you please help review and merge it? Thanks.
Best,
Aaron
-Original Message-
From: Liu, Zhiguang
Sent: Monday, April 1, 2024 10:06 AM
To: Li, Aaron ; devel@edk2.groups.io
Cc: Bi, Dandan ; Liming Gao ;
Liu, Yun Y ; Yao, Jiewen ; Ni, Ray
; Kinney, Michael D
Subject: RE: [PATCH v2 1/1] MdeModulePkg/AcpiTableDxe: PCD switch to avoid
using ACPI reclaim memory
Reviewed-by: Zhiguang Liu
> -Original Message-
> From: Li, Aaron
> Sent: Tuesday, March 26, 2024 3:58 PM
> To: devel@edk2.groups.io
> Cc: Liu, Zhiguang ; Bi, Dandan
> ; Liming Gao ; Liu, Yun Y
> ; Yao, Jiewen ; Ni, Ray
> ; Kinney, Michael D
> Subject: [PATCH v2 1/1] MdeModulePkg/AcpiTableDxe: PCD switch to avoid
> using ACPI reclaim memory
>
> UEFI spec defined ACPI Tables at boot time can be contained in memory of
> type EfiACPIReclaimMemory or EfiAcpiMemoryNVS, although InstallAcpiTable
> with AcpiTableProtocol will only allocate memory with type
> EfiACPIReclaimMemory (Except FACS).
>
> This patch provides an optional method controlled by PCD to avoid using
> EfiACPIReclaimMemory, by setting the PCD PcdNoACPIReclaimMemory to
> TRUE, all ACPI allocated memory will use EfiAcpiMemoryNVS instead.
>
> Cc: Zhiguang Liu
> Cc: Dandan Bi
> Cc: Liming Gao
> Cc: Liu Yun
> Cc: Jiewen Yao
> Cc: Ray Ni
> Cc: Michael D Kinney
> Signed-off-by: Aaron Li
> ---
> MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 37
> +++-
> MdeModulePkg/MdeModulePkg.dec| 7
> MdeModulePkg/MdeModulePkg.uni| 8 +
> MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf| 1 +
> 4 files changed, 45 insertions(+), 8 deletions(-)
>
> diff --git a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
> b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
> index e09bc9b704f5..080768033cfa 100644
> --- a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
> +++ b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
> @@ -340,6 +340,7 @@ ReallocateAcpiTableBuffer (
>EFI_ACPI_TABLE_INSTANCE TempPrivateData;
>EFI_STATUS Status;
>UINT64 CurrentData;
> + EFI_MEMORY_TYPE AcpiAllocateMemoryType;
>
>CopyMem (&TempPrivateData, AcpiTableInstance, sizeof
> (EFI_ACPI_TABLE_INSTANCE));
>//
> @@ -359,6 +360,12 @@ ReallocateAcpiTableBuffer (
> NewMaxTableNumber * sizeof (UINT32);
>}
>
> + if (PcdGetBool (PcdNoACPIReclaimMemory)) {
> +AcpiAllocateMemoryType = EfiACPIMemoryNVS; } else {
> +AcpiAllocateMemoryType = EfiACPIReclaimMemory; }
> +
>if (mAcpiTableAllocType != AllocateAnyPages) {
> //
> // Allocate memory in the lower 32 bit of address range for @@ -372,13
> +379,13 @@ ReallocateAcpiTableBuffer (
> PageAddress = 0x;
> Status = gBS->AllocatePages (
> mAcpiTableAllocType,
> - EfiACPIReclaimMemory,
> + AcpiAllocateMemoryType,
> EFI_SIZE_TO_PAGES (TotalSize),
> &PageAddress
> );
>} else {
> Status = gBS->AllocatePool (
> -EfiACPIReclaimMemory,
> +AcpiAllocateMemoryType,
> TotalSize,
> (VOID **)&Pointer
> );
> @@ -512,6 +519,7 @@ AddTableToList (
>EFI_PHYSICAL_ADDRESS AllocPhysAddress;
>UINT64Buffer64;
>BOOLEAN AddToRsdt;
> + EFI_MEMORY_TYPE AcpiAllocateMemoryType;
>
>//
>// Check for invalid input parameters @@ -550,6 +558,12 @@
> AddTableToList (
>CurrentTableList->TableSize = CurrentTableSize;
>CurrentTableList->PoolAllocation = FALSE;
>
> + if (PcdGetBool (PcdNoACPIReclaimMemory)) {
> +AcpiAllocateMemoryType = EfiACPIMemoryNVS; } else {
> +AcpiAllocateMemoryType = EfiACPIReclaimMemory; }
> +
>//
>// Allocation memory type depends on the type of the table
>//
> @@ -585,7 +599,7 @@ AddTableToList (
> // such as AArch64 that allocate multiples of 64 KB
> //
> Status = gBS->AllocatePool (
> -EfiACPIReclaimMemory,
> +AcpiAllocateMemoryType,
> CurrentTableList->TableSize,
> (VOID **)&CurrentTableList->Table
> );
> @@ -596,7 +610,7 @@ AddTableToList (
> //
> Status = gBS->AllocatePages (
> mAcpiTableAllocType,
> -EfiACPIReclaimMemory,
> +AcpiAllocateMemoryType,
> EFI_SIZE_TO_PAGES (CurrentTableList->TableSize),
> &AllocPhysAddress
> );
> @@ -1944,6 +1958,7 @@ AcpiTableAcpiTableConstructor (
>UINTN RsdpTableSize;
>UINT8 *Pointer;
>EFI_
Re: [edk2-devel] Is there a way to create filesystem in UEFI Shell ?
On Sat, Mar 30, 2024 at 06:10 AM, Andrew Fish wrote: > > You can make a ReadOnly file system out of contents on an FV (Firmware > Volume): > https://github.com/tianocore/edk2/tree/master/MdeModulePkg/Universal/FvSimpleFileSystemDxe > > FV is defined in the PI Spec as a layout for flash that contains files, > but no directories. > Hi Andrew, I forgot to mention earlier, that I'm developing for RISC-V architecture. It seems like the semihosting lib in edk2 does not have support for RISC-V yet. Thanks for the FvSimpleFileSystemDxe suggestion. Actually, I'm trying to TFTP "initramfs" (1MB) and "linux.efi" (25MB) into a filesystem. So, it requires to support write to the filesystem. Do you have other suggestions? Thanks! =) John -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117275): https://edk2.groups.io/g/devel/message/117275 Mute This Topic: https://groups.io/mt/105212723/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] Is there a way to create filesystem in UEFI Shell ?
Hi Michael, Thanks for the tool recommendation. However, the tools are useful for x86, arm, and IPF platforms. I'm working on a RISC-V platform. I wanted to compile the tools for RISC-V, but the link is not found: https://edk.tianocore.org/files/documents/16/347/file_347.dat/EDK%20Build_0_2.pdf (This link is located in ReleaseNote.txt) Do you know if there are similar tools that can be use in RISC-V platform? Thanks! =) John -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117276): https://edk2.groups.io/g/devel/message/117276 Mute This Topic: https://groups.io/mt/105212723/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms V2] MinPlatformPkg: Corret AcpiProcessorUid in MADT
Change AcpiProcessorUid in CpuApicIdOrderTable to
the index in MpService regardless of disabled core.
Let's take a simple example:
There are 2 enabled cores and 1 disabled core.
APICID Index in MpService
0x_0
0x_0010(disbaled) 1
0x_00402
With current implementation, the results of the x2apic
structure entries in MADT are:
MADT Entry APICID AcpiProcessorUid
0 0x_ 0
1 0x_0040 1
The AcpiProcessorUid will be associated with the
processor device defined in DSDT/SSDT. To make sure
the x2apic structure entries in MADT can be mapped to
the right processor devices in DSDT, the AcpiProcessorUid
of the second x2apic structure entry in MADT should
be kept as 2, which is the core index in MpService.
Signed-off-by: Dun Tan
Cc: Ray Ni
Cc: Jason Lou
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Liming Gao
Cc: Eric Dong
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index 2a833ec99c..f6ea7454d3 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -190,7 +190,7 @@ CreateCpuLocalApicInTable (
//
for (Socket = 0; Socket < FixedPcdGet32 (PcdMaxCpuSocketCount); Socket++) {
for (CurrProcessor = 0, Index = 0; CurrProcessor < mNumberOfCpus;
CurrProcessor++) {
- if (CpuApicIdOrderTable[CurrProcessor].Flags &&
(CpuApicIdOrderTable[CurrProcessor].SocketNum == Socket)) {
+ if (CpuApicIdOrderTable[CurrProcessor].SocketNum == Socket) {
CpuApicIdOrderTable[CurrProcessor].AcpiProcessorUid =
(CpuApicIdOrderTable[CurrProcessor].SocketNum << mNumOfBitShift) + Index;
Index++;
}
--
2.31.1.windows.1
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[edk2-devel] [edk2-platforms V2 0/3] MinPlatformPkg: Sort ApicIdOrderTable by special rules
This patch set is to sort ApicIdOrderTable by following special rules: 1. Make sure BSP is the first entry. 2. For APs, big core first, then small core. With this implementation, BIOS can present cores in order of relative performance in MADT. Linux OS would schedule cores by the order that they are presented in the MADT LocalX2ApicStruct entries. Then Linux OS would think of this as relative performance order. This implementation can benefit the linux os usage case. Dun Tan (3): MinPlatformPkg: Remove the global variable mForceX2ApicId MinPlatformPkg: Get CoreType for all cores MinPlatformPkg: Sort ApicIdOrderTable by special rules Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 123 +-- 1 file changed, 109 insertions(+), 14 deletions(-) -- 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117278): https://edk2.groups.io/g/devel/message/117278 Mute This Topic: https://groups.io/mt/105259122/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms V2 1/3] MinPlatformPkg: Remove the global variable mForceX2ApicId
This global variable mForceX2ApicId is not assigned
to any value in code and will be initialized to 0 when
the driver is loaded. So remove the global variable
and related code that will not be executed.
Signed-off-by: Dun Tan
Cc: Ray Ni
Cc: Jason Lou
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Liming Gao
Cc: Eric Dong
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index 2a833ec99c..62a7da290a 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -53,7 +53,6 @@ VOID *mLocalTable[] = {
EFI_ACPI_TABLE_PROTOCOL *mAcpiTable;
UINT32 mNumOfBitShift = 6;
-BOOLEAN mForceX2ApicId;
BOOLEAN mX2ApicEnabled;
EFI_MP_SERVICES_PROTOCOL*mMpService;
@@ -163,14 +162,6 @@ CreateCpuLocalApicInTable (
CpuIdMapPtr->Thread = ProcessorInfoBuffer.Location.Thread;
CpuIdMapPtr->Flags = ((ProcessorInfoBuffer.StatusFlag &
PROCESSOR_ENABLED_BIT) != 0);
CpuIdMapPtr->SocketNum = ProcessorInfoBuffer.Location.Package;
-
- //update processorbitMask
- if (CpuIdMapPtr->Flags == 1) {
-if (mForceX2ApicId) {
- CpuIdMapPtr->SocketNum&= 0x7;
- CpuIdMapPtr->AcpiProcessorUid &= 0xFF; //keep lower 8bit due to use
Proc obj in dsdt
-}
- }
} else { //not enabled
CpuIdMapPtr->ApicId = (UINT32)-1;
CpuIdMapPtr->Thread = (UINT32)-1;
@@ -1537,7 +1528,6 @@ InstallAcpiPlatform (
}
DEBUG ((DEBUG_INFO, "mX2ApicEnabled - 0x%x\n", mX2ApicEnabled));
- DEBUG ((DEBUG_INFO, "mForceX2ApicId - 0x%x\n", mForceX2ApicId));
// support up to 64 threads/socket
AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 1, &mNumOfBitShift, NULL, NULL, NULL);
--
2.31.1.windows.1
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[edk2-devel] [edk2-platforms V2 2/3] MinPlatformPkg: Get CoreType for all cores
Add a new field CoreType in EFI_CPU_ID_ORDER_MAP
and get CoreType for all cores.
Signed-off-by: Dun Tan
Cc: Ray Ni
Cc: Jason Lou
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Liming Gao
Cc: Eric Dong
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 50
++
1 file changed, 46 insertions(+), 4 deletions(-)
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index 62a7da290a..1fa70e3df9 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -18,6 +18,7 @@ typedef struct {
UINT32 Flags;
UINT32 SocketNum;
UINT32 Thread;
+ UINT8CoreType;
} EFI_CPU_ID_ORDER_MAP;
//
@@ -71,15 +72,16 @@ DebugDisplayReOrderTable (
{
UINT32 Index;
- DEBUG ((DEBUG_INFO, "Index AcpiProcId ApicId Thread Flags Skt\n"));
+ DEBUG ((DEBUG_INFO, "Index AcpiProcId ApicId Thread Flags Skt
CoreType\n"));
for (Index = 0; Index < mNumberOfCpus; Index++) {
-DEBUG ((DEBUG_INFO, " %02d 0x%02X 0x%02X %d %d
%d\n",
+DEBUG ((DEBUG_INFO, " %02d 0x%02X 0x%02X %d %d
%d 0x%x\n",
Index,
CpuApicIdOrderTable[Index].AcpiProcessorUid,
CpuApicIdOrderTable[Index].ApicId,
CpuApicIdOrderTable[Index].Thread,
CpuApicIdOrderTable[Index].Flags,
- CpuApicIdOrderTable[Index].SocketNum));
+ CpuApicIdOrderTable[Index].SocketNum,
+ CpuApicIdOrderTable[Index].CoreType));
}
}
@@ -130,6 +132,31 @@ AppendCpuMapTableEntry (
}
+/**
+ Get CPU core type.
+
+ @param[in] CpuApicIdOrderTable Point to a buffer which will be
filled in Core type information.
+**/
+VOID
+EFIAPI
+CollectCpuCoreType (
+ IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable
+ )
+{
+ UINTNApNumber;
+ EFI_STATUS Status;
+ CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX NativeModelIdAndCoreTypeEax;
+
+ Status = mMpService->WhoAmI (
+ mMpService,
+ &ApNumber
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ AsmCpuidEx (CPUID_HYBRID_INFORMATION, CPUID_HYBRID_INFORMATION_MAIN_LEAF,
&NativeModelIdAndCoreTypeEax.Uint32, NULL, NULL, NULL);
+ CpuApicIdOrderTable[ApNumber].CoreType =
(UINT8)NativeModelIdAndCoreTypeEax.Bits.CoreType;
+}
+
/**
Collect all processors information and create a Cpu Apic Id table.
@@ -146,8 +173,23 @@ CreateCpuLocalApicInTable (
UINT32CurrProcessor;
EFI_CPU_ID_ORDER_MAP *CpuIdMapPtr;
UINT32Socket;
+ UINT32CpuidMaxInput;
- Status = EFI_SUCCESS;
+ Status = EFI_SUCCESS;
+
+ AsmCpuid (CPUID_SIGNATURE, &CpuidMaxInput, NULL, NULL, NULL);
+ if (CpuidMaxInput >= CPUID_HYBRID_INFORMATION) {
+CollectCpuCoreType (CpuApicIdOrderTable);
+mMpService->StartupAllAPs (
+ mMpService, // This
+ (EFI_AP_PROCEDURE) CollectCpuCoreType,// Procedure
+ TRUE, // SingleThread
+ NULL, // WaitEvent
+ 0,//
TimeoutInMicrosecsond
+ CpuApicIdOrderTable, //
ProcedureArgument
+ NULL // FailedCpuList
+ );
+ }
for (CurrProcessor = 0, Index = 0; CurrProcessor < mNumberOfCpus;
CurrProcessor++, Index++) {
Status = mMpService->GetProcessorInfo (
--
2.31.1.windows.1
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[edk2-devel] [edk2-platforms V2 3/3] MinPlatformPkg: Sort ApicIdOrderTable by special rules
Sort ApicIdOrderTable by following special rules:
1. Make sure BSP is the first entry.
2. For APs, big core first, then small core.
With this implementation, BIOS can present cores in order
of relative performance in MADT. Linux OS would schedule
cores by the order that they are presented in the MADT
LocalX2ApicStruct entries.Then Linux OS would think of
this as relative performance order. This implementation
can benefit the linux os usage case.
Signed-off-by: Dun Tan
Cc: Ray Ni
Cc: Jason Lou
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Liming Gao
Cc: Eric Dong
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 63
+++
1 file changed, 63 insertions(+)
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index 1fa70e3df9..389df48824 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -132,6 +132,62 @@ AppendCpuMapTableEntry (
}
+/**
+ Sort CpuApicIdOrderTable based on the following rules:
+ 1.Make sure BSP is the first entry.
+ 2.Big core first, then small core.
+
+ @param[in] CpuApicIdOrderTable Pointer to EFI_CPU_ID_ORDER_MAP
+ @param[in] CountNumber to EFI_CPU_ID_ORDER_MAP
+ @param[in] BspIndex BSP index
+**/
+VOID
+SortApicIdOrderTable (
+ IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable,
+ IN UINTN Count,
+ IN UINTN BspIndex
+ )
+{
+ UINTN Index;
+ UINTN SubIndex;
+ EFI_CPU_ID_ORDER_MAP SortBuffer;
+
+ //
+ // Put BSP at the first entry.
+ //
+ if (BspIndex != 0) {
+CopyMem (&SortBuffer, &CpuApicIdOrderTable[BspIndex], sizeof
(EFI_CPU_ID_ORDER_MAP));
+CopyMem (&CpuApicIdOrderTable[1], CpuApicIdOrderTable, (BspIndex) * sizeof
(EFI_CPU_ID_ORDER_MAP));
+CopyMem (CpuApicIdOrderTable, &SortBuffer, sizeof (EFI_CPU_ID_ORDER_MAP));
+ }
+
+ //
+ // If there are more than 2 cores, perform insertion sort for rest cores
except the bsp in first entry
+ // to move big cores in front of small cores.
+ // Also the original order based on the MpService index inside big cores and
small cores are retained.
+ //
+ for (Index = 2; Index < Count; Index++) {
+if (CpuApicIdOrderTable[Index].CoreType == CPUID_CORE_TYPE_INTEL_ATOM) {
+ continue;
+}
+
+CopyMem (&SortBuffer, &CpuApicIdOrderTable[Index], sizeof
(EFI_CPU_ID_ORDER_MAP));
+
+for (SubIndex = Index - 1; SubIndex >= 1; SubIndex--) {
+ if (CpuApicIdOrderTable[SubIndex].CoreType ==
CPUID_CORE_TYPE_INTEL_ATOM) {
+CopyMem (&CpuApicIdOrderTable[SubIndex + 1],
&CpuApicIdOrderTable[SubIndex], sizeof (EFI_CPU_ID_ORDER_MAP));
+ } else {
+//
+// Except the BSP, all cores in front of SubIndex must be big cores.
+//
+break;
+ }
+}
+
+CopyMem (&CpuApicIdOrderTable[SubIndex + 1], &SortBuffer, sizeof
(EFI_CPU_ID_ORDER_MAP));
+ }
+}
+
/**
Get CPU core type.
@@ -174,6 +230,7 @@ CreateCpuLocalApicInTable (
EFI_CPU_ID_ORDER_MAP *CpuIdMapPtr;
UINT32Socket;
UINT32CpuidMaxInput;
+ UINTN BspIndex;
Status = EFI_SUCCESS;
@@ -198,6 +255,10 @@ CreateCpuLocalApicInTable (
&ProcessorInfoBuffer
);
+if ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_AS_BSP_BIT) != 0) {
+ BspIndex = Index;
+}
+
CpuIdMapPtr = (EFI_CPU_ID_ORDER_MAP *) &CpuApicIdOrderTable[Index];
if ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) != 0) {
CpuIdMapPtr->ApicId = (UINT32)ProcessorInfoBuffer.ProcessorId;
@@ -230,6 +291,8 @@ CreateCpuLocalApicInTable (
}
}
+ SortApicIdOrderTable (CpuApicIdOrderTable, mNumberOfCpus, BspIndex);
+
DEBUG ((DEBUG_INFO, "::ACPI:: APIC ID Order Table Init. mNumOfBitShift =
%x\n", mNumOfBitShift));
DebugDisplayReOrderTable (CpuApicIdOrderTable);
--
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