On Wed, Aug 28, 2013 at 4:02 PM, H. Peter Anvin <h...@zytor.com> wrote: > On 08/28/2013 10:35 AM, Anthony Liguori wrote: >> Yes, it was originally designed with the 16TB limit in mind. >> >> PCI doesn't support 64-bit PIO operations so it would have required a >> high/low register and additional magic. >> > > s/PCI/x86/
Ack. Although I wonder if there is a device out there that actually expects 64-bit writes to a register in an PIO region... > "Additional magic" is needed only if atomic changes are necessary, but > in this case this is stuff that is set up during early configuration and > so isn't an issue. The "additional magic" needed in that case is latch > logic - the write to the low part doesn't actually take effect until the > high part is written. Well in this case, writing to the PFN is what causes the queue to be initialized, there isn't a separate status register for this purpose. Since it's a PIO region, we tried hard to keep the common case within a 32-byte region and since config space is after the virtio-pci registers, we tried to keep it as small as possible to maximize available config space. Regards, Anthony Liguori > > -hpa >
