"Xie, Huawei" <huawei....@intel.com> writes: > If this is the case, one possible fix would be: > Write two continuous 32bit DWORD to combine a 64bit address > Use the upper 12 bits of PFN val to indicate if it is combined write > In this way, we wouldn't break other virtio driver, register layout > and only need a few lines of modification.
Note that (with OASIS) we are currently working on a v1.0 of the virtio spec. I recommend the OASIS virtio-dev mailing list ( https://www.oasis-open.org/mlmanage/ ) and in particular the thread on Michael Tsirkin's proposal on using PCI capabilities: https://lists.oasis-open.org/archives/virtio-comment/201308/msg00087.html Cheers, Rusty.
