On Monday 11 January 2010, Michel Catudal wrote: > That is correct. As for the watchdog, once you enable it you can no > longer debug as it keep reseting.
Isn't there an STM32-specific register to prevent the watchdog from counting while the core is in debug halt state? That's the solution I'm used to seeing on other cores. And I thought I saw docs for at least one Cortex-M3 core saying they had that solution. Maybe it wasn't STM32. > I will test this on the weekend to see if this is still true. > Right now for debugging I have conditional that disables the watchdog if I > want to debug. > I have the same problem with IAR so that is not an openocd problem. Of course, entirely disabling the watchdog can work too! I do that with WFI: if debugging, just busy-wait in the idle task. Otherwise the clock gating prevents me from talking to the core; it's idle most of the time, after all! - Dave _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
