On Tuesday 12 January 2010, Audrius Urmanavicius wrote:
> > Thing is, a watchdog is a global constraint device, so I don't see how
> > guarding it like that only for critical sections would help.
> 
> 
> ("mission critical section" of algorithm should not be confused here 
> with "code critical section", e.g. surrounded by resource locking 
> primitives).

Yeah, there are many types of critical section.


> The project contained a software PID controller, and I halted core in a 
> state when PID's output was quickly ramping up - PWM output had duty 
> cycle close to 100%. As I manually debug-halted core,

I think this is a good cautionary example of why halt-mode debugging
is sometimes undesirable.

A more visceral example is a saw controller ... if halted, it might
not be able to say "NO!  Not the fingers!"

Currently, OpenOCD does not support monitor mode debugging.  Most of
the ARM targets support it.  And I think I even saw docs on a Cortex-M3
part which included a debug monitor in ROM (was it from NXP?); I'd not
be surprised to see some folk looking at how to suport monitor mode in
the context of OpenOCD.


>        PWM was still  
> running, this time uncontrolled with same high duty cycle. That blew up 
> quite expensive mechanical equipment, it took few days to repair it. 
> Right after that I added if()'s in code that turns off DBG_IWDG_STOP bit 
> when PID is away from set point by some value, preventing halting core 
> without immediate WDG reset. Manipulation of this bit at run-time has no 
> consequences for normal flow of operation nor WDG, except when halting. 
> If someone happens to halt core again in critical part - MCU would just 
> merely reboot and switch off its outputs.

Yes, good example.  In fact, I think I'll update section 5.6 of the
User's Guide with some of your examples.  (That's "stuff you might
want to change to make debugging your code work better with JTAG".)

Thanks!

- Dave

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