David Brownell wrote:
>> Back to your question: I tried all of the four signal options, and
>> /basically/ all of them work. I can attach log files if needed.
>>
>> "none" and "trst_only"  seem to be the best options -- only one reset,
>> or reset-and-immediate-halt, as expected.
> 
> Said differently:  STM32 can use the current Cortex-M3 NVIC reset
> logic with no problems.  Good to know.

Nice!

> (Most of the Stellaris parts don't have a TRST signal.  You might
> double check to see if your board even uses it.  If not, "none" is
> your best answer.  It's the OpenOCD default, too.)
> 

Yes, my board has a standard 20-pin JTAG header. Line 3 is wired to 
NJTRST of the CPU, line 15 goes to the system reset.

>> "srst_only" and "trst_and_srst" give double-resets and run-before-halts.
> 
> Pretty much like some of the Stellaris parts.  The issue there
> is that SRST is resetting some of the debug logic, but that's
> supposed to be left untouched ... according to ARM.  You might
> want to consult ST, or the STM32 docs (and errata) to see if
> this is viewed as an erratum or just a variance from how ARM
> says things should work.

At least the "high-density device limitations" for my STM32F103VE 
deosn't seem to list any reset problems:

   http://www.st.com/stonline/products/literature/es/14732.pdf

>> But "trst_and_srst" is defined as the default in stm32.cfg .. perhaps
>> it's just the wrong reset type?!
> 
> The stm32.cfg shouldn't specify a reset type at all, since
> the right configuration depends on what the *board* wires up.
> Send a patch in ... :)

I'll try to do some more testing (flashing, gdb, etc.) tomorrow and send 
in a patch if everything works.

> There are a handful of targets that can't be debugged without
> both SRST and TRST; those are the only ones with any business
> providing such a config option in a target config file.

Hmm, 49 of 77 target files specify a reset type ;)
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