David Brownell wrote:
>> Even "reset halt" will let the CPU run for some amount of time
>> (e.g. enough to print a Hello-World string to the serial port..).
>
> Now *that* is a bug. And one that I suspect is specific to STM32, or
> at least to your particular chip, since I've not observed it on my
> tiny sample of Stellaris chips.
>
> What happens if you tell OpenOCD not to use SRST? The Cortex-M3 can
> reset using NVIC, without SRST. It has two NVIC resets ... see
> cortex_m3_assert_reset().
Well.. the whole reset stuff seems like black magic to me anyways. The
documentation says that there's a gazillion of possible ways to reset:
4 signals: none, trst_only, srst_only, trst_and_srst
4 combinations: seperate, combined, srst_pulls_trst, trst_pulls_srst
2 gates: srst_gates_jtag, srst_nogate
2 TRST type: trst_push_pull, trst_open_drain
2 SRST type: srst_push_pull, srst_open_drain
makes 128 different combinations, not counting the various _width and
_delay tuneables. Are all of them useful? And tested?
Back to your question: I tried all of the four signal options, and
/basically/ all of them work. I can attach log files if needed.
"none" and "trst_only" seem to be the best options -- only one reset,
or reset-and-immediate-halt, as expected.
"srst_only" and "trst_and_srst" give double-resets and run-before-halts.
But "trst_and_srst" is defined as the default in stm32.cfg .. perhaps
it's just the wrong reset type?!
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