On Sun, May 24, 2009 at 8:55 PM, Xiaofan Chen <xiaof...@gmail.com> wrote:
> On Sun, May 24, 2009 at 7:03 PM, Michael Fischer <fische...@t-online.de> 
> wrote:
>
>> Attached is the main.hex file which should work with the lpc2148 without
>> the calc_checksum key. LED1 and LED2 are flashing.
>
> Yes this works well with my V3 Black Jlink. The two LEDs are flashing now.
> I updated to the latest SVN with your updated lpc2148.cfg.
>
> I will try some other hex files. Thanks a lot for debugging the problems for 
> me.
>

So I used a big hex file from JCWren's example.
http://jcwren.com/arm/packages/LPC2148_Demo_v144.tgz

OpenOCD does not seem to work.
1) The resultant device is only partial working. There is a virtual com
port now but I can not talk to with gtkterm/cutecom.
2) And it seems to have reset/halt problem.

Maybe you can give it a try.

I will also try it with a V6 yellow J-Link tomorrow.

mc...@ubuntu904:~/Desktop/build/openocd/jlinkv3/flash$ openocd -f jlink.cfg
Open On-Chip Debugger 0.2.0-in-development (2009-05-24-21:41) svn:1906


BUGS? Read http://svn.berlios.de/svnroot/repos/openocd/trunk/BUGS


$URL: svn://svn.berlios.de/openocd/trunk/src/openocd.c $
30 kHz
Info : J-Link compiled Feb 20 2006 18:20:20 -- Update --
Info : JLink caps 0x3
Info : JLink hw version 30000
Info : Vref = 3.285 TCK = 1 TDI = 0 TDO = 0 TMS = 0 SRST = 1 TRST = 255

Info : J-Link JTAG Interface ready
Info : JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f
(Manufacturer: 0x787, Part: 0xf1f0, Version: 0x4)
Info : JTAG Tap/device matched
Warn : DBGACK set while target was in unknown state. Reset or initialize target.
target state: halted
target halted in Thumb state due to breakpoint, current mode: Supervisor
cpsr: 0xa00000f3 pc: 0x7fffd2c4
30 kHz
Info : JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f
(Manufacturer: 0x787, Part: 0xf1f0, Version: 0x4)
Info : JTAG Tap/device matched
Warn : srst pulls trst - can not reset into halted mode. Issuing halt
after reset.
target state: halted
target halted in Thumb state due to debug-request, current mode: Supervisor
cpsr: 0xa00000f3 pc: 0x7fffd2c0
requesting target halt and executing a soft reset
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0xa00000d3 pc: 0x00000000
1500 kHz
Info : accepting 'telnet' connection from 0
     TapName            | Enabled |   IdCode      Expected    IrLen
IrCap  IrMask Instr
---|--------------------|---------|------------|------------|------|------|------|---------
 0 | lpc2148.cpu        |    Y    | 0x4f1f0f0f | 0x4f1f0f0f | 0x04 |
0x01 | 0x0f | 0x0c
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0xa00000d3 pc: 0x00000000
Warn : Verification will fail since checksum in image(0xe59ff004)
written to flash was different from calculated vector
checksum(0xb9205f88).
Warn : To remove this warning modify build tools on developer PC to
inject correct LPC vector checksum.
wrote 232748 byte from file lpc2148.hex in 27.502781s (8.264363 kb/s)
30 kHz
Error: JTAG communication failure, check connection, JTAG interface,
target power etc.
Error: trying to validate configured JTAG chain anyway...
Error: Could not validate JTAG scan chain, IR mismatch, scan returned
0x00. tap=lpc2148.cpu pos=0 expected 0x1 got 0
Warn : Could not validate JTAG chain, continuing anyway...
Warn : value captured during scan didn't pass the requested check:
Warn : captured: 0x00 check_value: 0x01 check_mask: 0x0F
Runtime error, file "embedded:startup.tcl", line 177:
    examine-fails: -104
Runtime error, file "command.c", line 453:
    Error: timed out while waiting for target halted
Runtime error, file "command.c", line 453:
    target state: running
Error: timed out while waiting for target halted
Runtime error, file "command.c", line 453:
    ^C

mc...@ubuntu904:~/Desktop/build/openocd/jlinkv3/flash$ telnet localhost 4444
Trying ::1...
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> scan_chain
     TapName            | Enabled |   IdCode      Expected    IrLen
IrCap  IrMask Instr
---|--------------------|---------|------------|------------|------|------|------|---------
 0 | lpc2148.cpu        |    Y    | 0x4f1f0f0f | 0x4f1f0f0f | 0x04 |
0x01 | 0x0f | 0x0c
> halt
> poll
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0xa00000d3 pc: 0x00000000
> flash write_image lpc2148.hex 0x0
Verification will fail since checksum in image(0xe59ff004) written to
flash was different from calculated vector checksum(0xb9205f88).
To remove this warning modify build tools on developer PC to inject
correct LPC vector checksum.
wrote 232748 byte from file lpc2148.hex in 27.502781s (8.264363 kb/s)
> reset
30 kHz
JTAG communication failure, check connection, JTAG interface, target power etc.
trying to validate configured JTAG chain anyway...
Could not validate JTAG scan chain, IR mismatch, scan returned 0x00.
tap=lpc2148.cpu pos=0 expected 0x1 got 0
Could not validate JTAG chain, continuing anyway...
value captured during scan didn't pass the requested check:
captured: 0x00 check_value: 0x01 check_mask: 0x0F
Runtime error, file "embedded:startup.tcl", line 177:
    examine-fails: -104
in procedure 'ocd_process_reset'
called at file "embedded:startup.tcl", line 176
Runtime error, file "command.c", line 453:

> halt
timed out while waiting for target halted
Runtime error, file "command.c", line 453:

> poll
target state: running
> halt
timed out while waiting for target halted
Runtime error, file "command.c", line 453:

> Connection closed by foreign host.

The script is based on yours.
mc...@ubuntu904:~/Desktop/build/openocd/jlinkv3/flash$ cat jlink.cfg
#
# For more information about the configuration files, take a
# look at the "Open On-Chip Debugger (openocd)" documentation.
#
# This config file was tested with OpenOCD version r1888+patch
#

# daemon configuration
telnet_port 4444
gdb_port 3333
tcl_port 6666

# tell gdb our flash memory map
# and enable flash programming
gdb_memory_map enable
gdb_flash_program enable

#########################################################
#
# Interface, if you want to use an other interface
# you must replace this section here.
#

#interface ft2232
#ft2232_device_desc "Amontec JTAGkey A"
#ft2232_layout jtagkey
#ft2232_vid_pid 0x0403 0xcff8

#########################################################

source [find interface/jlink.cfg]

#
# Target section, this example was tested with an
# Olimex LPC-P2148 board
#

# Start slow, speed up after reset
jtag_khz 30

if { [info exists CHIPNAME] } { 
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME lpc2148
}

if { [info exists ENDIAN] } {
   set _ENDIAN $ENDIAN
} else {
   set _ENDIAN little
}

if { [info exists CPUTAPID ] } {
   set _CPUTAPID $CPUTAPID
} else {
   set _CPUTAPID 0x4f1f0f0f
}

jtag_nsrst_delay 200
jtag_ntrst_delay 200

# NOTE!!! LPCs need reset pulled while RTCK is low. 0 to activate
# JTAG, power-on reset is not enough, i.e. you need to perform a
# reset before being able to talk to the LPC2148, attach is not possible.

reset_config trst_and_srst srst_pulls_trst

jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
-expected-id $_CPUTAPID

set _TARGETNAME [format "%s.cpu" $_CHIPNAME]

target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position
$_TARGETNAME -variant arm7tdmi-s_r4

$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000
-work-area-size 0x4000 -work-area-backup 0

$_TARGETNAME configure -event reset-start {
        jtag_khz 30
}

$_TARGETNAME configure -event reset-init {
        # Force target into ARM state.
        soft_reset_halt

        # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
        # "User Flash Mode" where interrupt vectors are _not_ remapped,
        # and reside in flash instead).
        #
        # See section 7.1 on page 32 ("Memory Mapping control register") in
        # "UM10139: Volume 1: LPC214x User Manual", Rev. 02 -- 25 July 2006.
        # 
http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc2141.lpc2142.lpc2144.lpc2146.lpc2148.pdf
        mwb 0xE01FC040 0x01

        jtag_khz 1500
}

# flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock>
[calc_checksum]
#flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 calc_checksum
flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765 calc_checksum

#########################################################

init

reset init




-- 
Xiaofan http://mcuee.blogspot.com
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