This looks good. Just some nits below.
On Fri, Sep 4, 2015 at 9:47 PM, Bas Nieuwenhuizen
<b...@basnieuwenhuizen.nl> wrote:
> As the alignment requirements can be 32 KiB or more, also adding
> an aligned buffer creation function.
>
> Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
> ---
> src/gallium/drivers/radeon/r600_buffer_common.c | 20 +++++++++++
> src/gallium/drivers/radeon/r600_pipe_common.h | 6 ++++
> src/gallium/drivers/radeon/r600_texture.c | 18 ++++++++++
> src/gallium/drivers/radeon/radeon_winsys.h | 5 +++
> src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 48
> ++++++++++++++++++++++---
> 5 files changed, 92 insertions(+), 5 deletions(-)
>
> diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c
> b/src/gallium/drivers/radeon/r600_buffer_common.c
> index cb9809f..d869856 100644
> --- a/src/gallium/drivers/radeon/r600_buffer_common.c
> +++ b/src/gallium/drivers/radeon/r600_buffer_common.c
> @@ -422,6 +422,26 @@ struct pipe_resource *r600_buffer_create(struct
> pipe_screen *screen,
> return &rbuffer->b.b;
> }
>
> +struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
> + unsigned bind,
> + unsigned usage,
> + unsigned size,
> + unsigned alignment)
> +{
> + struct pipe_resource buffer;
Missing space after the declaration.
> + memset(&buffer, 0, sizeof buffer);
> + buffer.target = PIPE_BUFFER;
> + buffer.format = PIPE_FORMAT_R8_UNORM;
> + buffer.bind = bind;
> + buffer.usage = usage;
> + buffer.flags = 0;
> + buffer.width0 = size;
> + buffer.height0 = 1;
> + buffer.depth0 = 1;
> + buffer.array_size = 1;
> + return r600_buffer_create(screen, &buffer, alignment);
This should use tabs for indentation.
> +}
> +
> struct pipe_resource *
> r600_buffer_from_user_memory(struct pipe_screen *screen,
> const struct pipe_resource *templ,
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
> b/src/gallium/drivers/radeon/r600_pipe_common.h
> index d22c230..4bbecca 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> @@ -212,6 +212,7 @@ struct r600_texture {
> struct r600_fmask_info fmask;
> struct r600_cmask_info cmask;
> struct r600_resource *cmask_buffer;
> + struct r600_resource *dcc_buffer;
> unsigned cb_color_info; /* fast clear enable
> bit */
> unsigned color_clear_value[2];
>
> @@ -488,6 +489,11 @@ bool r600_init_resource(struct r600_common_screen
> *rscreen,
> struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
> const struct pipe_resource *templ,
> unsigned alignment);
> +struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
> + unsigned bind,
> + unsigned usage,
> + unsigned size,
> + unsigned alignment);
> struct pipe_resource *
> r600_buffer_from_user_memory(struct pipe_screen *screen,
> const struct pipe_resource *templ,
> diff --git a/src/gallium/drivers/radeon/r600_texture.c
> b/src/gallium/drivers/radeon/r600_texture.c
> index 89f18fb..46e735e 100644
> --- a/src/gallium/drivers/radeon/r600_texture.c
> +++ b/src/gallium/drivers/radeon/r600_texture.c
> @@ -268,6 +268,7 @@ static void r600_texture_destroy(struct pipe_screen
> *screen,
> if (rtex->cmask_buffer != &rtex->resource) {
> pipe_resource_reference((struct
> pipe_resource**)&rtex->cmask_buffer, NULL);
> }
> + pipe_resource_reference((struct pipe_resource**)&rtex->dcc_buffer,
> NULL);
> pb_reference(&resource->buf, NULL);
> FREE(rtex);
> }
> @@ -482,6 +483,20 @@ static void r600_texture_alloc_cmask_separate(struct
> r600_common_screen *rscreen
> rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
> }
>
> +static void vi_texture_alloc_dcc_separate(struct r600_common_screen *rscreen,
> + struct r600_texture *rtex)
> +{
> + rtex->dcc_buffer = (struct r600_resource *)
> + r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
> + PIPE_USAGE_DEFAULT,
> rtex->surface.dcc_size, rtex->surface.dcc_alignment);
> + if (rtex->dcc_buffer == NULL) {
> + return;
> + }
> +
> + r600_screen_clear_buffer(rscreen, &rtex->dcc_buffer->b.b, 0,
> rtex->surface.dcc_size,
> + 0xFFFFFFFF, true);
> +}
> +
> static unsigned r600_texture_get_htile_size(struct r600_common_screen
> *rscreen,
> struct r600_texture *rtex)
> {
> @@ -621,6 +636,9 @@ r600_texture_create_object(struct pipe_screen *screen,
> return NULL;
> }
> }
> + if(rscreen->chip_class >= VI && rtex->surface.dcc_allowed) {
Missing space after "if".
> + vi_texture_alloc_dcc_separate(rscreen, rtex);
> + }
> }
>
> /* Now create the backing buffer. */
> diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
> b/src/gallium/drivers/radeon/radeon_winsys.h
> index 00accd5..20ee38d 100644
> --- a/src/gallium/drivers/radeon/radeon_winsys.h
> +++ b/src/gallium/drivers/radeon/radeon_winsys.h
> @@ -292,6 +292,7 @@ struct radeon_surf_level {
> uint32_t nblk_z;
> uint32_t pitch_bytes;
> uint32_t mode;
> + uint64_t dcc_offset;
> };
>
> struct radeon_surf {
> @@ -327,6 +328,10 @@ struct radeon_surf {
> uint32_t stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
> uint32_t pipe_config;
> uint32_t num_banks;
> +
> + uint64_t dcc_size;
> + uint64_t dcc_alignment;
> + bool dcc_allowed;
> };
>
> struct radeon_winsys {
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
> b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
> index 358df38..5296695 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
> @@ -175,7 +175,9 @@ static int compute_level(struct amdgpu_winsys *ws,
> struct radeon_surf *surf, bool is_stencil,
> unsigned level, unsigned type, bool compressed,
> ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
> - ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut)
> + ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
> + ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
> + ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut)
> {
> struct radeon_surf_level *surf_level;
> ADDR_E_RETURNCODE ret;
> @@ -248,6 +250,30 @@ static int compute_level(struct amdgpu_winsys *ws,
> surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
>
> surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
> +
> + if(surf->dcc_allowed) {
Missing space after "if".
Marek
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