The DCC fast clear for multisampled textures is still disabled
as that does not work correctly yet.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
---
 src/gallium/drivers/radeon/r600_texture.c      | 3 ++-
 src/gallium/drivers/radeonsi/si_blit.c         | 2 +-
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 3 +--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 6a4bb59..6848009 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1308,7 +1308,8 @@ void evergreen_do_fast_color_clear(struct 
r600_common_context *rctx,
 
                evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
 
-               if(tex->dcc_buffer && 
vi_is_dcc_clear_allowed(fb->cbufs[i]->format, color, &dcc_reset_value)) {
+               if(tex->dcc_buffer && tex->resource.b.b.nr_samples <= 1 &&
+                  vi_is_dcc_clear_allowed(fb->cbufs[i]->format, color, 
&dcc_reset_value)) {
                        rctx->clear_buffer(&rctx->b, &tex->dcc_buffer->b.b,
                                        0, tex->surface.dcc_size, 
dcc_reset_value, true);
 
diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 1c08329..b2e7f62 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -307,7 +307,7 @@ static void si_blit_decompress_color(struct pipe_context 
*ctx,
                if (first_layer == 0 && last_layer == max_layer) {
                        rtex->dirty_level_mask &= ~(1 << level);
 
-                       if(need_dcc_decompress)
+                       if(rtex->fmask.size || need_dcc_decompress)
                                rtex->dcc_compressed_level_mask &= ~(1 << 
level);
                }
        }
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 5296695..2550a56 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -354,8 +354,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
    AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = surf->nsamples;
    AddrSurfInfoIn.tileIndex = -1;
    
-   surf->dcc_allowed =  !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && 
-                        !compressed && AddrDccIn.numSamples <= 1 &&
+   surf->dcc_allowed =  !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && 
!compressed &&
                         !(surf->flags & RADEON_SURF_SCANOUT);
 
    /* Set the micro tile type. */
-- 
2.5.1

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