The flags to be enabled in the control registers have been taken from
Catalyst traces.
Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
---
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
src/gallium/drivers/radeon/r600_texture.c | 2 ++
src/gallium/drivers/radeon/r600d_common.h | 1 +
src/gallium/drivers/radeonsi/si_blit.c | 16 ++++++++++++----
src/gallium/drivers/radeonsi/si_pipe.c | 2 ++
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_state.c | 27 +++++++++++++++++++++++----
src/gallium/drivers/radeonsi/sid.h | 1 +
8 files changed, 43 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index f05318f..dac270e 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -244,6 +244,7 @@ struct r600_surface {
unsigned cb_color_dim; /* EG only */
unsigned cb_color_pitch; /* EG and later */
unsigned cb_color_slice; /* EG and later */
+ unsigned cb_dcc_base; /* VI and later */
unsigned cb_color_attrib; /* EG and later */
unsigned cb_dcc_control; /* VI and later */
unsigned cb_color_fmask; /* CB_COLORn_FMASK (EG and later) or
CB_COLORn_FRAG (r600) */
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index 46e735e..017f5e7 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -495,6 +495,8 @@ static void vi_texture_alloc_dcc_separate(struct
r600_common_screen *rscreen,
r600_screen_clear_buffer(rscreen, &rtex->dcc_buffer->b.b, 0,
rtex->surface.dcc_size,
0xFFFFFFFF, true);
+
+ rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
}
static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
diff --git a/src/gallium/drivers/radeon/r600d_common.h
b/src/gallium/drivers/radeon/r600d_common.h
index 115042d..a3d182c 100644
--- a/src/gallium/drivers/radeon/r600d_common.h
+++ b/src/gallium/drivers/radeon/r600d_common.h
@@ -202,6 +202,7 @@
#define EG_S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17)
#define SI_S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 13)
+#define VI_S_028C70_DCC_ENABLE(x) (((x) & 0x1) << 28)
/*CIK+*/
#define R_0300FC_CP_STRMOUT_CNTL 0x0300FC
diff --git a/src/gallium/drivers/radeonsi/si_blit.c
b/src/gallium/drivers/radeonsi/si_blit.c
index 13bb457..98913e5 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -264,7 +264,7 @@ static void si_blit_decompress_color(struct pipe_context
*ctx,
return;
for (level = first_level; level <= last_level; level++) {
- if (!(rtex->dirty_level_mask & (1 << level)))
+ if (!(rtex->dirty_level_mask & (1 << level)) &&
!(rtex->dcc_compressed_level_mask & (1 << level)))
continue;
/* The smaller the mipmap level, the less layers there are
@@ -274,6 +274,7 @@ static void si_blit_decompress_color(struct pipe_context
*ctx,
for (layer = first_layer; layer <= checked_last_layer; layer++)
{
struct pipe_surface *cbsurf, surf_tmpl;
+ void * custom_blend;
surf_tmpl.format = rtex->resource.b.b.format;
surf_tmpl.u.tex.level = level;
@@ -281,10 +282,17 @@ static void si_blit_decompress_color(struct pipe_context
*ctx,
surf_tmpl.u.tex.last_layer = layer;
cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b,
&surf_tmpl);
+ if(rtex->fmask.size) {
+ custom_blend = sctx->custom_blend_decompress;
+ } else if(rtex->dcc_buffer) {
+ /* also eliminates the fast clear if necessary
*/
+ custom_blend =
sctx->custom_blend_dcc_decompress;
+ } else {
+ custom_blend = sctx->custom_blend_fastclear;
+ }
+
si_blitter_begin(ctx, SI_DECOMPRESS);
- util_blitter_custom_color(sctx->blitter, cbsurf,
- rtex->fmask.size ?
sctx->custom_blend_decompress :
-
sctx->custom_blend_fastclear);
+ util_blitter_custom_color(sctx->blitter, cbsurf,
custom_blend);
si_blitter_end(ctx);
pipe_surface_reference(&cbsurf, NULL);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 7dbb2e3..a5525ac 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -67,6 +67,8 @@ static void si_destroy_context(struct pipe_context *context)
sctx->b.b.delete_blend_state(&sctx->b.b,
sctx->custom_blend_decompress);
if (sctx->custom_blend_fastclear)
sctx->b.b.delete_blend_state(&sctx->b.b,
sctx->custom_blend_fastclear);
+ if (sctx->custom_blend_dcc_decompress)
+ sctx->b.b.delete_blend_state(&sctx->b.b,
sctx->custom_blend_dcc_decompress);
util_unreference_framebuffer_state(&sctx->framebuffer.state);
if (sctx->blitter)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index d9c7871..66c66c8 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -159,6 +159,7 @@ struct si_context {
void *custom_blend_resolve;
void *custom_blend_decompress;
void *custom_blend_fastclear;
+ void *custom_blend_dcc_decompress;
void *pstipple_sampler_state;
struct si_screen *screen;
struct pipe_fence_handle *last_gfx_fence;
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index faef2ee..5c9c866 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1915,8 +1915,19 @@ static void si_initialize_color_surface(struct
si_context *sctx,
surf->cb_color_info = color_info;
surf->cb_color_attrib = color_attrib;
- if (sctx->b.chip_class >= VI)
- surf->cb_dcc_control = S_028C78_OVERWRITE_COMBINER_DISABLE(1);
+ if (sctx->b.chip_class >= VI) {
+
+ surf->cb_dcc_control = S_028C78_KEY_CLEAR_ENABLE(1) |
+ S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(2) |
+ S_028C78_INDEPENDENT_64B_BLOCKS(1);
+
+ if(rtex->dcc_buffer) {
+ uint64_t dcc_offset =
rtex->surface.level[level].dcc_offset;
+
+ surf->cb_dcc_base = (rtex->dcc_buffer->gpu_address +
dcc_offset) >> 8;
+ }
+ }
+
if (rtex->fmask.size) {
surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
@@ -2245,6 +2256,12 @@ static void si_emit_framebuffer_state(struct si_context
*sctx, struct r600_atom
RADEON_PRIO_COLOR_META);
}
+ if (tex->dcc_buffer && tex->dcc_buffer != &tex->resource) {
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
+ tex->dcc_buffer, RADEON_USAGE_READWRITE,
+ RADEON_PRIO_COLOR_META);
+ }
+
radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i *
0x3C,
sctx->b.chip_class >= VI ? 14 : 13);
radeon_emit(cs, cb->cb_color_base); /*
R_028C60_CB_COLOR0_BASE */
@@ -2262,7 +2279,7 @@ static void si_emit_framebuffer_state(struct si_context
*sctx, struct r600_atom
radeon_emit(cs, tex->color_clear_value[1]); /*
R_028C90_CB_COLOR0_CLEAR_WORD1 */
if (sctx->b.chip_class >= VI)
- radeon_emit(cs, 0); /* R_028C94_CB_COLOR0_DCC_BASE
*/
+ radeon_emit(cs, cb->cb_dcc_base); /*
R_028C94_CB_COLOR0_DCC_BASE */
}
/* set CB_COLOR1_INFO for possible dual-src blending */
if (i == 1 && state->cbufs[0] &&
@@ -3052,6 +3069,7 @@ void si_init_state_functions(struct si_context *sctx)
sctx->custom_blend_resolve = si_create_blend_custom(sctx,
V_028808_CB_RESOLVE);
sctx->custom_blend_decompress = si_create_blend_custom(sctx,
V_028808_CB_FMASK_DECOMPRESS);
sctx->custom_blend_fastclear = si_create_blend_custom(sctx,
V_028808_CB_ELIMINATE_FAST_CLEAR);
+ sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx,
V_028808_CB_DCC_DECOMPRESS);
sctx->b.b.set_clip_state = si_set_clip_state;
sctx->b.b.set_scissor_states = si_set_scissor_states;
@@ -3386,7 +3404,8 @@ static void si_init_config(struct si_context *sctx)
if (sctx->b.chip_class >= VI) {
si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
-
S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1));
+
S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
+ S_028424_OVERWRITE_COMBINER_WATERMARK(4));
si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
}
diff --git a/src/gallium/drivers/radeonsi/sid.h
b/src/gallium/drivers/radeonsi/sid.h
index 4bb2457..f642f03 100644
--- a/src/gallium/drivers/radeonsi/sid.h
+++ b/src/gallium/drivers/radeonsi/sid.h
@@ -5473,6 +5473,7 @@
#define V_028808_CB_ELIMINATE_FAST_CLEAR 0x02
#define V_028808_CB_RESOLVE 0x03
#define V_028808_CB_FMASK_DECOMPRESS 0x05
+#define V_028808_CB_DCC_DECOMPRESS 0x06
#define S_028808_ROP3(x) (((x) &
0xFF) << 16)
#define G_028808_ROP3(x) (((x) >>
16) & 0xFF)
#define C_028808_ROP3
0xFF00FFFF
--
2.5.1
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