From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_state.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index f7878ed2367..b50182582c6 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3343,24 +3343,24 @@ static void si_emit_msaa_config(struct si_context *sctx)
7, /* 8x MSAA */
8, /* 16x MSAA */
};
unsigned log_samples = util_logbase2(setup_samples);
unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
unsigned log_ps_iter_samples =
util_logbase2(util_next_power_of_two(ps_iter_samples));
radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
radeon_emit(cs, sc_line_cntl |
- S_028BDC_EXPAND_LINE_WIDTH(1)); /*
CM_R_028BDC_PA_SC_LINE_CNTL */
+ S_028BDC_EXPAND_LINE_WIDTH(1)); /*
R_028BDC_PA_SC_LINE_CNTL */
radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
- S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /*
CM_R_028BE0_PA_SC_AA_CONFIG */
+ S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /*
R_028BE0_PA_SC_AA_CONFIG */
if (sctx->framebuffer.nr_samples > 1) {
radeon_set_context_reg(cs, R_028804_DB_EQAA,
S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
@@ -3369,22 +3369,22 @@ static void si_emit_msaa_config(struct si_context *sctx)
} else if (sctx->smoothing_enabled) {
radeon_set_context_reg(cs, R_028804_DB_EQAA,
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
sc_mode_cntl_1);
}
} else {
radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
- radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
- radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
+ radeon_emit(cs, sc_line_cntl); /* R_028BDC_PA_SC_LINE_CNTL */
+ radeon_emit(cs, 0); /* R_028BE0_PA_SC_AA_CONFIG */
radeon_set_context_reg(cs, R_028804_DB_EQAA,
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
sc_mode_cntl_1);
}
/* GFX9: Flush DFSM when the AA mode changes. */
if (sctx->screen->dfsm_allowed) {
--
2.17.0
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