From: Marek Olšák <marek.ol...@amd.com>
radeon_surf contains almost everything.
---
src/gallium/drivers/radeonsi/si_blit.c | 6 +-
src/gallium/drivers/radeonsi/si_clear.c | 2 +-
src/gallium/drivers/radeonsi/si_descriptors.c | 10 ++--
src/gallium/drivers/radeonsi/si_pipe.h | 17 +-----
src/gallium/drivers/radeonsi/si_state.c | 38 ++++++------
src/gallium/drivers/radeonsi/si_texture.c | 60 ++++++-------------
6 files changed, 46 insertions(+), 87 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_blit.c
b/src/gallium/drivers/radeonsi/si_blit.c
index 1cbd26f46e0..6f4cd1f9044 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -463,21 +463,21 @@ static void si_blit_decompress_color(struct si_context
*sctx,
if (need_dcc_decompress) {
custom_blend = sctx->custom_blend_dcc_decompress;
assert(rtex->dcc_offset);
/* disable levels without DCC */
for (int i = first_level; i <= last_level; i++) {
if (!vi_dcc_enabled(rtex, i))
level_mask &= ~(1 << i);
}
- } else if (rtex->fmask.size) {
+ } else if (rtex->surface.fmask_size) {
custom_blend = sctx->custom_blend_fmask_decompress;
} else {
custom_blend = sctx->custom_blend_eliminate_fastclear;
}
sctx->decompression_enabled = true;
while (level_mask) {
unsigned level = u_bit_scan(&level_mask);
@@ -521,21 +521,21 @@ static void si_blit_decompress_color(struct si_context
*sctx,
sctx->decompression_enabled = false;
si_make_CB_shader_coherent(sctx, rtex->buffer.b.b.nr_samples,
vi_dcc_enabled(rtex, first_level));
}
static void
si_decompress_color_texture(struct si_context *sctx, struct r600_texture *tex,
unsigned first_level, unsigned last_level)
{
/* CMASK or DCC can be discarded and we can still end up here. */
- if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
+ if (!tex->cmask.size && !tex->surface.fmask_size && !tex->dcc_offset)
return;
si_blit_decompress_color(sctx, tex, first_level, last_level, 0,
util_max_layer(&tex->buffer.b.b, first_level),
false);
}
static void
si_decompress_sampler_color_textures(struct si_context *sctx,
struct si_samplers *textures)
@@ -842,21 +842,21 @@ static void si_decompress_subresource(struct pipe_context
*ctx,
* by dirtying the framebuffer.
*/
if (sctx->framebuffer.state.zsbuf &&
sctx->framebuffer.state.zsbuf->u.tex.level == level &&
sctx->framebuffer.state.zsbuf->texture == tex)
si_update_fb_dirtiness_after_rendering(sctx);
si_decompress_depth(sctx, rtex, planes,
level, level,
first_layer, last_layer);
- } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
+ } else if (rtex->surface.fmask_size || rtex->cmask.size ||
rtex->dcc_offset) {
/* If we've rendered into the framebuffer and it's a blitting
* source, make sure the decompression pass is invoked
* by dirtying the framebuffer.
*/
for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
{
if (sctx->framebuffer.state.cbufs[i] &&
sctx->framebuffer.state.cbufs[i]->u.tex.level ==
level &&
sctx->framebuffer.state.cbufs[i]->texture == tex) {
si_update_fb_dirtiness_after_rendering(sctx);
break;
diff --git a/src/gallium/drivers/radeonsi/si_clear.c
b/src/gallium/drivers/radeonsi/si_clear.c
index 0de51488f59..8ecd47fea9b 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -570,21 +570,21 @@ static void si_clear(struct pipe_context *ctx, unsigned
buffers,
/* These buffers cannot use fast clear, make sure to disable
expansion. */
for (unsigned i = 0; i < fb->nr_cbufs; i++) {
struct r600_texture *tex;
/* If not clearing this buffer, skip. */
if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) ||
!fb->cbufs[i])
continue;
tex = (struct r600_texture *)fb->cbufs[i]->texture;
- if (tex->fmask.size == 0)
+ if (tex->surface.fmask_size == 0)
tex->dirty_level_mask &= ~(1 <<
fb->cbufs[i]->u.tex.level);
}
}
if (zstex &&
si_htile_enabled(zstex, zsbuf->u.tex.level) &&
zsbuf->u.tex.first_layer == 0 &&
zsbuf->u.tex.last_layer == util_max_layer(&zstex->buffer.b.b, 0)) {
/* TC-compatible HTILE only supports depth clears to 0 or 1. */
if (buffers & PIPE_CLEAR_DEPTH &&
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 9f2433a5b72..1d14c9df1e1 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -460,36 +460,36 @@ static void si_set_sampler_view_desc(struct si_context
*sctx,
si_set_mutable_tex_desc_fields(sctx->screen, rtex,
sview->base_level_info,
sview->base_level,
sview->base.u.tex.first_level,
sview->block_width,
is_separate_stencil,
desc);
}
- if (!is_buffer && rtex->fmask.size) {
+ if (!is_buffer && rtex->surface.fmask_size) {
memcpy(desc + 8, sview->fmask_state, 8*4);
} else {
/* Disable FMASK and bind sampler state in [12:15]. */
memcpy(desc + 8, null_texture_descriptor, 4*4);
if (sstate)
si_set_sampler_state_desc(sstate, sview,
is_buffer ? NULL : rtex,
desc + 12);
}
}
static bool color_needs_decompression(struct r600_texture *rtex)
{
- return rtex->fmask.size ||
+ return rtex->surface.fmask_size ||
(rtex->dirty_level_mask &&
(rtex->cmask.size || rtex->dcc_offset));
}
static bool depth_needs_decompression(struct r600_texture *rtex)
{
/* If the depth/stencil texture is TC-compatible, no decompression
* will be done. The decompression function will only flush DB caches
* to make it coherent with shaders. That's necessary because the driver
* doesn't flush DB caches in any other case.
@@ -707,27 +707,27 @@ static void si_set_shader_image_desc(struct si_context
*ctx,
unsigned level = view->u.tex.level;
unsigned width, height, depth, hw_level;
bool uses_dcc = vi_dcc_enabled(tex, level);
unsigned access = view->access;
/* Clear the write flag when writes can't occur.
* Note that DCC_DECOMPRESS for MSAA doesn't work in some cases,
* so we don't wanna trigger it.
*/
if (tex->is_depth ||
- (!fmask_desc && tex->fmask.size != 0)) {
+ (!fmask_desc && tex->surface.fmask_size != 0)) {
assert(!"Z/S and MSAA image stores are not supported");
access &= ~PIPE_IMAGE_ACCESS_WRITE;
}
assert(!tex->is_depth);
- assert(fmask_desc || tex->fmask.size == 0);
+ assert(fmask_desc || tex->surface.fmask_size == 0);
if (uses_dcc && !skip_decompress &&
(view->access & PIPE_IMAGE_ACCESS_WRITE ||
!vi_dcc_formats_compatible(res->b.b.format,
view->format))) {
/* If DCC can't be disabled, at least decompress it.
* The decompression is relatively cheap if the surface
* has been decompressed already.
*/
if (!si_texture_disable_dcc(ctx, tex))
si_decompress_dcc(ctx, tex);
@@ -973,21 +973,21 @@ static void si_bind_sampler_states(struct pipe_context
*ctx,
*/
struct si_sampler_view *sview =
(struct si_sampler_view *)samplers->views[slot];
struct r600_texture *tex = NULL;
if (sview && sview->base.texture &&
sview->base.texture->target != PIPE_BUFFER)
tex = (struct r600_texture *)sview->base.texture;
- if (tex && tex->fmask.size)
+ if (tex && tex->surface.fmask_size)
continue;
si_set_sampler_state_desc(sstates[i], sview, tex,
desc->list + desc_slot * 16 + 12);
sctx->descriptors_dirty |= 1u <<
si_sampler_and_image_descriptors_idx(shader);
}
}
/* BUFFER RESOURCES */
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index 27efc5099f0..b5caf944759 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -223,48 +223,37 @@ struct r600_resource {
bool texture_handle_allocated;
bool image_handle_allocated;
};
struct r600_transfer {
struct threaded_transfer b;
struct r600_resource *staging;
unsigned offset;
};
-struct r600_fmask_info {
- uint64_t offset;
- uint64_t size;
- unsigned alignment;
- unsigned pitch_in_pixels;
- unsigned bank_height;
- unsigned slice_tile_max;
- unsigned tile_mode_index;
- unsigned tile_swizzle;
-};
-
struct r600_cmask_info {
uint64_t offset;
uint64_t size;
unsigned alignment;
unsigned slice_tile_max;
uint64_t base_address_reg;
};
struct r600_texture {
struct r600_resource buffer;
struct radeon_surf surface;
uint64_t size;
struct r600_texture *flushed_depth_texture;
/* Colorbuffer compression and fast clear. */
- struct r600_fmask_info fmask;
+ uint64_t fmask_offset;
struct r600_cmask_info cmask;
struct r600_resource *cmask_buffer;
uint64_t dcc_offset; /* 0 = disabled */
unsigned cb_color_info; /* fast clear enable bit
*/
unsigned color_clear_value[2];
unsigned last_msaa_resolve_target_micro_mode;
unsigned num_level0_transfers;
/* Depth buffer compression and fast clear. */
uint64_t htile_offset;
@@ -1223,24 +1212,20 @@ void si_update_vs_viewport_state(struct si_context
*ctx);
void si_init_viewport_functions(struct si_context *ctx);
/* r600_texture.c */
bool si_prepare_for_dma_blit(struct si_context *sctx,
struct r600_texture *rdst,
unsigned dst_level, unsigned dstx,
unsigned dsty, unsigned dstz,
struct r600_texture *rsrc,
unsigned src_level,
const struct pipe_box *src_box);
-void si_texture_get_fmask_info(struct si_screen *sscreen,
- struct r600_texture *rtex,
- unsigned nr_samples,
- struct r600_fmask_info *out);
void si_texture_get_cmask_info(struct si_screen *sscreen,
struct r600_texture *rtex,
struct r600_cmask_info *out);
void si_eliminate_fast_color_clear(struct si_context *sctx,
struct r600_texture *rtex);
void si_texture_discard_cmask(struct si_screen *sscreen,
struct r600_texture *rtex);
bool si_init_flushed_depth_texture(struct pipe_context *ctx,
struct pipe_resource *texture,
struct r600_texture **staging);
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 0c4e6d08855..f7878ed2367 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2407,23 +2407,23 @@ static void si_initialize_color_surface(struct
si_context *sctx,
/* Intensity is implemented as Red, so treat it that way. */
color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
PIPE_SWIZZLE_1 ||
util_format_is_intensity(surf->base.format));
if (rtex->buffer.b.b.nr_samples > 1) {
unsigned log_samples =
util_logbase2(rtex->buffer.b.b.nr_samples);
color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
S_028C74_NUM_FRAGMENTS(log_samples);
- if (rtex->fmask.size) {
+ if (rtex->surface.fmask_size) {
color_info |= S_028C70_COMPRESSION(1);
- unsigned fmask_bankh =
util_logbase2(rtex->fmask.bank_height);
+ unsigned fmask_bankh =
util_logbase2(rtex->surface.u.legacy.fmask.bankh);
if (sctx->chip_class == SI) {
/* due to a hw bug, FMASK_BANK_HEIGHT must be
set on SI too */
color_attrib |=
S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
}
}
}
if (sctx->chip_class >= VI) {
unsigned max_uncompressed_block_size =
V_028C78_MAX_BLOCK_SIZE_256B;
@@ -2442,21 +2442,21 @@ static void si_initialize_color_surface(struct
si_context *sctx,
else if (rtex->surface.bpe == 2)
max_uncompressed_block_size =
V_028C78_MAX_BLOCK_SIZE_128B;
}
surf->cb_dcc_control =
S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
S_028C78_INDEPENDENT_64B_BLOCKS(1);
}
/* This must be set for fast clear to work without FMASK. */
- if (!rtex->fmask.size && sctx->chip_class == SI) {
+ if (!rtex->surface.fmask_size && sctx->chip_class == SI) {
unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
}
unsigned color_view =
S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
if (sctx->chip_class >= GFX9) {
unsigned mip0_depth = util_max_layer(&rtex->buffer.b.b, 0);
@@ -2657,21 +2657,21 @@ void si_update_fb_dirtiness_after_rendering(struct
si_context *sctx)
if (rtex->surface.has_stencil)
rtex->stencil_dirty_level_mask |= 1 <<
surf->u.tex.level;
}
unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
while (compressed_cb_mask) {
unsigned i = u_bit_scan(&compressed_cb_mask);
struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
struct r600_texture *rtex = (struct r600_texture*)surf->texture;
- if (rtex->fmask.size)
+ if (rtex->surface.fmask_size)
rtex->dirty_level_mask |= 1 << surf->u.tex.level;
if (rtex->dcc_gather_statistics)
rtex->separate_dcc_dirty = true;
}
}
static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state)
{
for (int i = 0; i < state->nr_cbufs; ++i) {
struct r600_surface *surf = NULL;
@@ -2829,21 +2829,21 @@ static void si_set_framebuffer_state(struct
pipe_context *ctx,
sctx->framebuffer.spi_shader_col_format_blend |=
surf->spi_shader_col_format_blend << (i * 4);
sctx->framebuffer.spi_shader_col_format_blend_alpha |=
surf->spi_shader_col_format_blend_alpha << (i * 4);
if (surf->color_is_int8)
sctx->framebuffer.color_is_int8 |= 1 << i;
if (surf->color_is_int10)
sctx->framebuffer.color_is_int10 |= 1 << i;
- if (rtex->fmask.size)
+ if (rtex->surface.fmask_size)
sctx->framebuffer.compressed_cb_mask |= 1 << i;
else
sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
if (rtex->surface.is_linear)
sctx->framebuffer.any_dst_linear = true;
if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
sctx->framebuffer.CB_has_shader_readable_metadata =
true;
@@ -2980,23 +2980,23 @@ static void si_emit_framebuffer_state(struct si_context
*sctx)
cb_color_base = tex->buffer.gpu_address >> 8;
cb_color_fmask = 0;
cb_color_cmask = tex->cmask.base_address_reg;
cb_dcc_base = 0;
cb_color_info = cb->cb_color_info | tex->cb_color_info;
cb_color_attrib = cb->cb_color_attrib;
if (cb->base.u.tex.level > 0)
cb_color_info &= C_028C70_FAST_CLEAR;
- if (tex->fmask.size) {
- cb_color_fmask = (tex->buffer.gpu_address +
tex->fmask.offset) >> 8;
- cb_color_fmask |= tex->fmask.tile_swizzle;
+ if (tex->surface.fmask_size) {
+ cb_color_fmask = (tex->buffer.gpu_address +
tex->fmask_offset) >> 8;
+ cb_color_fmask |= tex->surface.fmask_tile_swizzle;
}
/* Set up DCC. */
if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
bool is_msaa_resolve_dst = state->cbufs[0] &&
state->cbufs[0]->texture->nr_samples > 1 &&
state->cbufs[1] == &cb->base
&&
state->cbufs[1]->texture->nr_samples <= 1;
if (!is_msaa_resolve_dst)
@@ -3011,21 +3011,21 @@ static void si_emit_framebuffer_state(struct si_context
*sctx)
struct gfx9_surf_meta_flags meta;
if (tex->dcc_offset)
meta = tex->surface.u.gfx9.dcc;
else
meta = tex->surface.u.gfx9.cmask;
/* Set mutable surface parameters. */
cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
cb_color_base |= tex->surface.tile_swizzle;
- if (!tex->fmask.size)
+ if (!tex->surface.fmask_size)
cb_color_fmask = cb_color_base;
if (cb->base.u.tex.level > 0)
cb_color_cmask = cb_color_base;
cb_color_attrib |=
S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
S_028C74_RB_ALIGNED(meta.rb_aligned)
|
S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE
+ i * 0x3C, 15);
radeon_emit(cs, cb_color_base); /*
CB_COLOR0_BASE */
@@ -3051,41 +3051,41 @@ static void si_emit_framebuffer_state(struct si_context
*sctx)
const struct legacy_surf_level *level_info =
&tex->surface.u.legacy.level[cb->base.u.tex.level];
unsigned pitch_tile_max, slice_tile_max,
tile_mode_index;
unsigned cb_color_pitch, cb_color_slice,
cb_color_fmask_slice;
cb_color_base += level_info->offset >> 8;
/* Only macrotiled modes can set tile swizzle. */
if (level_info->mode == RADEON_SURF_MODE_2D)
cb_color_base |= tex->surface.tile_swizzle;
- if (!tex->fmask.size)
+ if (!tex->surface.fmask_size)
cb_color_fmask = cb_color_base;
if (cb->base.u.tex.level > 0)
cb_color_cmask = cb_color_base;
if (cb_dcc_base)
cb_dcc_base += level_info->dcc_offset >> 8;
pitch_tile_max = level_info->nblk_x / 8 - 1;
slice_tile_max = level_info->nblk_x *
level_info->nblk_y / 64 - 1;
tile_mode_index = si_tile_mode_index(tex,
cb->base.u.tex.level, false);
cb_color_attrib |=
S_028C74_TILE_MODE_INDEX(tile_mode_index);
cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
- if (tex->fmask.size) {
+ if (tex->surface.fmask_size) {
if (sctx->chip_class >= CIK)
- cb_color_pitch |=
S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
- cb_color_attrib |=
S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
- cb_color_fmask_slice =
S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
+ cb_color_pitch |=
S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
+ cb_color_attrib |=
S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
+ cb_color_fmask_slice =
S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
} else {
/* This must be set for fast clear to work
without FMASK. */
if (sctx->chip_class >= CIK)
cb_color_pitch |=
S_028C64_FMASK_TILE_MAX(pitch_tile_max);
cb_color_attrib |=
S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
cb_color_fmask_slice =
S_028C88_TILE_MAX(slice_tile_max);
}
radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE
+ i * 0x3C,
sctx->chip_class >= VI ? 14
: 13);
@@ -3729,24 +3729,24 @@ si_make_texture_descriptor(struct si_screen *screen,
*/
if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
if (first_level == last_level)
state[7] = C_008F30_MAX_ANISO_RATIO;
else
state[7] = 0xffffffff;
}
}
/* Initialize the sampler view for FMASK. */
- if (tex->fmask.size) {
+ if (tex->surface.fmask_size) {
uint32_t data_format, num_format;
- va = tex->buffer.gpu_address + tex->fmask.offset;
+ va = tex->buffer.gpu_address + tex->fmask_offset;
if (screen->info.chip_class >= GFX9) {
data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
switch (res->nr_samples) {
case 2:
num_format = V_008F14_IMG_FMASK_8_2_2;
break;
case 4:
num_format = V_008F14_IMG_FMASK_8_4_4;
break;
@@ -3766,21 +3766,21 @@ si_make_texture_descriptor(struct si_screen *screen,
break;
case 8:
data_format =
V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
break;
default:
unreachable("invalid nr_samples");
}
num_format = V_008F14_IMG_NUM_FORMAT_UINT;
}
- fmask_state[0] = (va >> 8) | tex->fmask.tile_swizzle;
+ fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
S_008F14_DATA_FORMAT_GFX6(data_format) |
S_008F14_NUM_FORMAT_GFX6(num_format);
fmask_state[2] = S_008F18_WIDTH(width - 1) |
S_008F18_HEIGHT(height - 1);
fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
S_008F1C_TYPE(si_tex_dim(screen, tex, target,
0));
@@ -3789,23 +3789,23 @@ si_make_texture_descriptor(struct si_screen *screen,
fmask_state[6] = 0;
fmask_state[7] = 0;
if (screen->info.chip_class >= GFX9) {
fmask_state[3] |=
S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
fmask_state[4] |= S_008F20_DEPTH(last_layer) |
S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
fmask_state[5] |=
S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
} else {
- fmask_state[3] |=
S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
+ fmask_state[3] |=
S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
-
S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
+
S_008F20_PITCH_GFX6(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
}
}
}
/**
* Create a sampler view.
*
* @param ctx context
* @param texture texture
diff --git a/src/gallium/drivers/radeonsi/si_texture.c
b/src/gallium/drivers/radeonsi/si_texture.c
index 3fd34af338d..81a70153f32 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -557,35 +557,35 @@ static void si_reallocate_texture_inplace(struct
si_context *sctx,
rtex->buffer.bo_size = new_tex->buffer.bo_size;
rtex->buffer.bo_alignment = new_tex->buffer.bo_alignment;
rtex->buffer.domains = new_tex->buffer.domains;
rtex->buffer.flags = new_tex->buffer.flags;
rtex->size = new_tex->size;
rtex->db_render_format = new_tex->db_render_format;
rtex->db_compatible = new_tex->db_compatible;
rtex->can_sample_z = new_tex->can_sample_z;
rtex->can_sample_s = new_tex->can_sample_s;
rtex->surface = new_tex->surface;
- rtex->fmask = new_tex->fmask;
+ rtex->fmask_offset = new_tex->fmask_offset;
rtex->cmask = new_tex->cmask;
rtex->cb_color_info = new_tex->cb_color_info;
rtex->last_msaa_resolve_target_micro_mode =
new_tex->last_msaa_resolve_target_micro_mode;
rtex->htile_offset = new_tex->htile_offset;
rtex->tc_compatible_htile = new_tex->tc_compatible_htile;
rtex->depth_cleared = new_tex->depth_cleared;
rtex->stencil_cleared = new_tex->stencil_cleared;
rtex->dcc_gather_statistics = new_tex->dcc_gather_statistics;
rtex->framebuffers_bound = new_tex->framebuffers_bound;
if (new_bind_flag == PIPE_BIND_LINEAR) {
assert(!rtex->htile_offset);
assert(!rtex->cmask.size);
- assert(!rtex->fmask.size);
+ assert(!rtex->surface.fmask_size);
assert(!rtex->dcc_offset);
assert(!rtex->is_depth);
}
r600_texture_reference(&new_tex, NULL);
p_atomic_inc(&sctx->screen->dirty_tex_counter);
}
static uint32_t si_get_bo_metadata_word1(struct si_screen *sscreen)
@@ -605,21 +605,21 @@ static void si_query_opaque_metadata(struct si_screen
*sscreen,
PIPE_SWIZZLE_W
};
uint32_t desc[8], i;
bool is_array = util_texture_is_array(res->target);
/* DRM 2.x.x doesn't support this. */
if (sscreen->info.drm_major != 3)
return;
assert(rtex->dcc_separate_buffer == NULL);
- assert(rtex->fmask.size == 0);
+ assert(rtex->surface.fmask_size == 0);
/* Metadata image format format version 1:
* [0] = 1 (metadata format identifier)
* [1] = (VENDOR_ID << 16) | PCI_ID
* [2:9] = image descriptor for the whole resource
* [2] is always 0, because the base address is cleared
* [9] is the DCC offset bits [39:8] from the beginning of
* the buffer
* [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
*/
@@ -838,52 +838,20 @@ static void si_texture_destroy(struct pipe_screen *screen,
r600_resource_reference(&rtex->cmask_buffer, NULL);
}
pb_reference(&resource->buf, NULL);
r600_resource_reference(&rtex->dcc_separate_buffer, NULL);
r600_resource_reference(&rtex->last_dcc_separate_buffer, NULL);
FREE(rtex);
}
static const struct u_resource_vtbl si_texture_vtbl;
-/* The number of samples can be specified independently of the texture. */
-void si_texture_get_fmask_info(struct si_screen *sscreen,
- struct r600_texture *rtex,
- unsigned nr_samples,
- struct r600_fmask_info *out)
-{
- if (sscreen->info.chip_class >= GFX9) {
- out->alignment = rtex->surface.fmask_alignment;
- out->size = rtex->surface.fmask_size;
- out->tile_swizzle = rtex->surface.fmask_tile_swizzle;
- return;
- }
-
- out->slice_tile_max = rtex->surface.u.legacy.fmask.slice_tile_max;
- out->tile_mode_index = rtex->surface.u.legacy.fmask.tiling_index;
- out->pitch_in_pixels = rtex->surface.u.legacy.fmask.pitch_in_pixels;
- out->bank_height = rtex->surface.u.legacy.fmask.bankh;
- out->tile_swizzle = rtex->surface.fmask_tile_swizzle;
- out->alignment = rtex->surface.fmask_alignment;
- out->size = rtex->surface.fmask_size;
-}
-
-static void si_texture_allocate_fmask(struct si_screen *sscreen,
- struct r600_texture *rtex)
-{
- si_texture_get_fmask_info(sscreen, rtex,
- rtex->buffer.b.b.nr_samples, &rtex->fmask);
-
- rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
- rtex->size = rtex->fmask.offset + rtex->fmask.size;
-}
-
void si_texture_get_cmask_info(struct si_screen *sscreen,
struct r600_texture *rtex,
struct r600_cmask_info *out)
{
unsigned pipe_interleave_bytes = sscreen->info.pipe_interleave_bytes;
unsigned num_pipes = sscreen->info.num_tile_pipes;
unsigned cl_width, cl_height;
if (sscreen->info.chip_class >= GFX9) {
out->alignment = rtex->surface.u.gfx9.cmask_alignment;
@@ -1042,24 +1010,24 @@ void si_print_texture_info(struct si_screen *sscreen,
if (sscreen->info.chip_class >= GFX9) {
u_log_printf(log, " Surf: size=%"PRIu64",
slice_size=%"PRIu64", "
"alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
rtex->surface.surf_size,
rtex->surface.u.gfx9.surf_slice_size,
rtex->surface.surf_alignment,
rtex->surface.u.gfx9.surf.swizzle_mode,
rtex->surface.u.gfx9.surf.epitch,
rtex->surface.u.gfx9.surf_pitch);
- if (rtex->fmask.size) {
+ if (rtex->surface.fmask_size) {
u_log_printf(log, " FMASK: offset=%"PRIu64",
size=%"PRIu64", "
"alignment=%u, swmode=%u, epitch=%u\n",
- rtex->fmask.offset,
+ rtex->fmask_offset,
rtex->surface.fmask_size,
rtex->surface.fmask_alignment,
rtex->surface.u.gfx9.fmask.swizzle_mode,
rtex->surface.u.gfx9.fmask.epitch);
}
if (rtex->cmask.size) {
u_log_printf(log, " CMask: offset=%"PRIu64",
size=%"PRIu64", "
"alignment=%u, rb_aligned=%u,
pipe_aligned=%u\n",
rtex->cmask.offset,
@@ -1097,26 +1065,28 @@ void si_print_texture_info(struct si_screen *sscreen,
return;
}
u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
"bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u,
scanout=%u\n",
rtex->surface.surf_size, rtex->surface.surf_alignment,
rtex->surface.u.legacy.bankw,
rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks,
rtex->surface.u.legacy.mtilea,
rtex->surface.u.legacy.tile_split,
rtex->surface.u.legacy.pipe_config,
(rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
- if (rtex->fmask.size)
+ if (rtex->surface.fmask_size)
u_log_printf(log, " FMask: offset=%"PRIu64", size=%"PRIu64",
alignment=%u, pitch_in_pixels=%u, "
"bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
- rtex->fmask.offset, rtex->fmask.size,
rtex->fmask.alignment,
- rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
- rtex->fmask.slice_tile_max,
rtex->fmask.tile_mode_index);
+ rtex->fmask_offset, rtex->surface.fmask_size,
rtex->surface.fmask_alignment,
+ rtex->surface.u.legacy.fmask.pitch_in_pixels,
+ rtex->surface.u.legacy.fmask.bankh,
+ rtex->surface.u.legacy.fmask.slice_tile_max,
+ rtex->surface.u.legacy.fmask.tiling_index);
if (rtex->cmask.size)
u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64",
alignment=%u, "
"slice_tile_max=%u\n",
rtex->cmask.offset, rtex->cmask.size,
rtex->cmask.alignment,
rtex->cmask.slice_tile_max);
if (rtex->htile_offset)
u_log_printf(log, " HTile: offset=%"PRIu64", size=%u, "
"alignment=%u, TC_compatible = %u\n",
@@ -1241,25 +1211,29 @@ si_texture_create_object(struct pipe_screen *screen,
SI_RESOURCE_FLAG_FLUSHED_DEPTH))) {
rtex->db_compatible = true;
if (!(sscreen->debug_flags & DBG(NO_HYPERZ)))
si_texture_allocate_htile(sscreen, rtex);
}
} else {
if (base->nr_samples > 1 &&
!buf &&
!(sscreen->debug_flags & DBG(NO_FMASK))) {
- si_texture_allocate_fmask(sscreen, rtex);
+ /* Allocate FMASK. */
+ rtex->fmask_offset = align64(rtex->size,
+
rtex->surface.fmask_alignment);
+ rtex->size = rtex->fmask_offset +
rtex->surface.fmask_size;
+
si_texture_allocate_cmask(sscreen, rtex);
rtex->cmask_buffer = &rtex->buffer;
- if (!rtex->fmask.size || !rtex->cmask.size) {
+ if (!rtex->surface.fmask_size || !rtex->cmask.size) {
FREE(rtex);
return NULL;
}
}
/* Shared textures must always set up DCC here.
* If it's not present, it will be disabled by
* apply_opaque_metadata later.
*/
if (rtex->surface.dcc_size &&
--
2.17.0
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