From: Marek Olšák <marek.ol...@amd.com>
---
src/amd/common/ac_surface.c | 20 +++++++++----------
src/amd/common/ac_surface.h | 10 +++-------
src/amd/vulkan/radv_image.c | 12 +++++------
src/gallium/drivers/radeonsi/si_texture.c | 16 +++++++--------
.../winsys/radeon/drm/radeon_drm_surface.c | 6 +++---
5 files changed, 30 insertions(+), 34 deletions(-)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 69a0c8a0f2f..5030d10242e 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -846,23 +846,23 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
fin.numSlices = AddrSurfInfoIn.numSlices;
fin.numSamples = AddrSurfInfoIn.numSamples;
fin.numFrags = AddrSurfInfoIn.numFrags;
fin.tileIndex = AddrSurfInfoOut.tileIndex;
fout.pTileInfo = &fmask_tile_info;
r = AddrComputeFmaskInfo(addrlib, &fin, &fout);
if (r)
return r;
- surf->u.legacy.fmask.size = fout.fmaskBytes;
- surf->u.legacy.fmask.alignment = fout.baseAlign;
- surf->u.legacy.fmask.tile_swizzle = 0;
+ surf->fmask_size = fout.fmaskBytes;
+ surf->fmask_alignment = fout.baseAlign;
+ surf->fmask_tile_swizzle = 0;
surf->u.legacy.fmask.slice_tile_max =
(fout.pitch * fout.height) / 64;
if (surf->u.legacy.fmask.slice_tile_max)
surf->u.legacy.fmask.slice_tile_max -= 1;
surf->u.legacy.fmask.tiling_index = fout.tileIndex;
surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
@@ -881,21 +881,21 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
xin.macroModeIndex = fout.macroModeIndex;
xin.pTileInfo = fout.pTileInfo;
xin.tileMode = fin.tileMode;
int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout);
if (r != ADDR_OK)
return r;
assert(xout.tileSwizzle <=
u_bit_consecutive(0, sizeof(surf->tile_swizzle)
* 8));
- surf->u.legacy.fmask.tile_swizzle = xout.tileSwizzle;
+ surf->fmask_tile_swizzle = xout.tileSwizzle;
}
}
/* Recalculate the whole DCC miptree size including disabled levels.
* This is what addrlib does, but calling addrlib would be a lot more
* complicated.
*/
if (surf->dcc_size && config->info.levels > 1) {
/* The smallest miplevels that are never compressed by DCC
* still read the DCC buffer via TC if the base level uses DCC,
@@ -1176,22 +1176,22 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
fin.numSlices = in->numSlices;
fin.numSamples = in->numSamples;
fin.numFrags = in->numFrags;
ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
if (ret != ADDR_OK)
return ret;
surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
surf->u.gfx9.fmask.epitch = fout.pitch - 1;
- surf->u.gfx9.fmask_size = fout.fmaskBytes;
- surf->u.gfx9.fmask_alignment = fout.baseAlign;
+ surf->fmask_size = fout.fmaskBytes;
+ surf->fmask_alignment = fout.baseAlign;
/* Compute tile swizzle for the FMASK surface. */
if (config->info.fmask_surf_index &&
fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
!(surf->flags & RADEON_SURF_SHAREABLE)) {
ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
xin.size =
sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
xout.size =
sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
@@ -1203,22 +1203,22 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
xin.resourceType = in->resourceType;
xin.format = in->format;
xin.numSamples = in->numSamples;
xin.numFrags = in->numFrags;
ret = Addr2ComputePipeBankXor(addrlib, &xin,
&xout);
if (ret != ADDR_OK)
return ret;
assert(xout.pipeBankXor <=
- u_bit_consecutive(0,
sizeof(surf->u.gfx9.fmask_tile_swizzle) * 8));
- surf->u.gfx9.fmask_tile_swizzle =
xout.pipeBankXor;
+ u_bit_consecutive(0,
sizeof(surf->fmask_tile_swizzle) * 8));
+ surf->fmask_tile_swizzle = xout.pipeBankXor;
}
}
/* CMASK */
if (in->swizzleMode != ADDR_SW_LINEAR) {
ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
@@ -1370,26 +1370,26 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
default:
assert(0);
}
surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
surf->num_dcc_levels = 0;
surf->surf_size = 0;
+ surf->fmask_size = 0;
surf->dcc_size = 0;
surf->htile_size = 0;
surf->htile_slice_size = 0;
surf->u.gfx9.surf_offset = 0;
surf->u.gfx9.stencil_offset = 0;
- surf->u.gfx9.fmask_size = 0;
surf->u.gfx9.cmask_size = 0;
/* Calculate texture layout information. */
r = gfx9_compute_miptree(addrlib, config, surf, compressed,
&AddrSurfInfoIn);
if (r)
return r;
/* Calculate texture layout information for stencil. */
if (surf->flags & RADEON_SURF_SBUFFER) {
@@ -1470,21 +1470,21 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
case ADDR_SW_VAR_Z_X:
surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
break;
default:
assert(0);
}
/* Temporary workaround to prevent VM faults and hangs. */
if (info->family == CHIP_VEGA12)
- surf->u.gfx9.fmask_size *= 8;
+ surf->fmask_size *= 8;
return 0;
}
int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
const struct ac_surf_config *config,
enum radeon_surf_mode mode,
struct radeon_surf *surf)
{
int r;
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index d0249684ad2..45fb8045e53 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -73,23 +73,20 @@ struct legacy_surf_level {
uint64_t offset;
uint32_t slice_size_dw; /* in dwords; max = 4GB / 4. */
uint32_t dcc_offset; /* relative offset within DCC mip
tree */
uint32_t dcc_fast_clear_size;
unsigned nblk_x:15;
unsigned nblk_y:15;
enum radeon_surf_mode mode:2;
};
struct legacy_surf_fmask {
- uint64_t size;
- unsigned alignment;
- unsigned tile_swizzle;
unsigned slice_tile_max; /* max 4M */
uint8_t tiling_index; /* max 31 */
uint8_t bankh; /* max 8 */
uint16_t pitch_in_pixels;
};
struct legacy_surf_layout {
unsigned bankw:4; /* max 8 */
unsigned bankh:4; /* max 8 */
unsigned mtilea:4; /* max 8 */
@@ -146,27 +143,23 @@ struct gfx9_surf_layout {
uint64_t surf_offset; /* 0 unless imported with an
offset */
/* The size of the 2D plane containing all mipmap levels. */
uint64_t surf_slice_size;
/* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
uint32_t offset[RADEON_SURF_MAX_LEVELS];
uint16_t dcc_pitch_max; /* (mip chain pitch - 1) */
uint64_t stencil_offset; /* separate stencil */
- uint64_t fmask_size;
uint64_t cmask_size;
- uint32_t fmask_alignment;
uint32_t cmask_alignment;
-
- uint8_t fmask_tile_swizzle;
};
struct radeon_surf {
/* Format properties. */
unsigned blk_w:4;
unsigned blk_h:4;
unsigned bpe:5;
/* Number of mipmap levels where DCC is enabled starting from level 0.
* Non-zero levels may be disabled due to alignment constraints, but not
* the first level.
@@ -192,29 +185,32 @@ struct radeon_surf {
* tail.
*
* Only these surfaces are allowed to set it:
* - color (if it doesn't have to be displayable)
* - DCC (same tile swizzle as color)
* - FMASK
* - CMASK if it's TC-compatible or if the gen is GFX9
* - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
*/
uint8_t tile_swizzle;
+ uint8_t fmask_tile_swizzle;
uint64_t surf_size;
+ uint64_t fmask_size;
/* DCC and HTILE are very small. */
uint32_t dcc_size;
uint32_t htile_size;
uint32_t htile_slice_size;
uint32_t surf_alignment;
+ uint32_t fmask_alignment;
uint32_t dcc_alignment;
uint32_t htile_alignment;
union {
/* R600-VI return values.
*
* Some of them can be set by the caller if certain parameters are
* desirable. The allocator will try to obey them.
*/
struct legacy_surf_layout legacy;
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 9df59e759aa..031250b1cb2 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -720,33 +720,33 @@ radv_init_metadata(struct radv_device *device,
}
/* The number of samples can be specified independently of the texture. */
static void
radv_image_get_fmask_info(struct radv_device *device,
struct radv_image *image,
unsigned nr_samples,
struct radv_fmask_info *out)
{
if (device->physical_device->rad_info.chip_class >= GFX9) {
- out->alignment = image->surface.u.gfx9.fmask_alignment;
- out->size = image->surface.u.gfx9.fmask_size;
- out->tile_swizzle = image->surface.u.gfx9.fmask_tile_swizzle;
+ out->alignment = image->surface.fmask_alignment;
+ out->size = image->surface.fmask_size;
+ out->tile_swizzle = image->surface.fmask_tile_swizzle;
return;
}
out->slice_tile_max = image->surface.u.legacy.fmask.slice_tile_max;
out->tile_mode_index = image->surface.u.legacy.fmask.tiling_index;
out->pitch_in_pixels = image->surface.u.legacy.fmask.pitch_in_pixels;
out->bank_height = image->surface.u.legacy.fmask.bankh;
- out->tile_swizzle = image->surface.u.legacy.fmask.tile_swizzle;
- out->alignment = image->surface.u.legacy.fmask.alignment;
- out->size = image->surface.u.legacy.fmask.size;
+ out->tile_swizzle = image->surface.fmask_tile_swizzle;
+ out->alignment = image->surface.fmask_alignment;
+ out->size = image->surface.fmask_size;
assert(!out->tile_swizzle || !image->shareable);
}
static void
radv_image_alloc_fmask(struct radv_device *device,
struct radv_image *image)
{
radv_image_get_fmask_info(device, image, image->info.samples,
&image->fmask);
diff --git a/src/gallium/drivers/radeonsi/si_texture.c
b/src/gallium/drivers/radeonsi/si_texture.c
index e072fbd0b4d..3fd34af338d 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -845,33 +845,33 @@ static void si_texture_destroy(struct pipe_screen *screen,
static const struct u_resource_vtbl si_texture_vtbl;
/* The number of samples can be specified independently of the texture. */
void si_texture_get_fmask_info(struct si_screen *sscreen,
struct r600_texture *rtex,
unsigned nr_samples,
struct r600_fmask_info *out)
{
if (sscreen->info.chip_class >= GFX9) {
- out->alignment = rtex->surface.u.gfx9.fmask_alignment;
- out->size = rtex->surface.u.gfx9.fmask_size;
- out->tile_swizzle = rtex->surface.u.gfx9.fmask_tile_swizzle;
+ out->alignment = rtex->surface.fmask_alignment;
+ out->size = rtex->surface.fmask_size;
+ out->tile_swizzle = rtex->surface.fmask_tile_swizzle;
return;
}
out->slice_tile_max = rtex->surface.u.legacy.fmask.slice_tile_max;
out->tile_mode_index = rtex->surface.u.legacy.fmask.tiling_index;
out->pitch_in_pixels = rtex->surface.u.legacy.fmask.pitch_in_pixels;
out->bank_height = rtex->surface.u.legacy.fmask.bankh;
- out->tile_swizzle = rtex->surface.u.legacy.fmask.tile_swizzle;
- out->alignment = rtex->surface.u.legacy.fmask.alignment;
- out->size = rtex->surface.u.legacy.fmask.size;
+ out->tile_swizzle = rtex->surface.fmask_tile_swizzle;
+ out->alignment = rtex->surface.fmask_alignment;
+ out->size = rtex->surface.fmask_size;
}
static void si_texture_allocate_fmask(struct si_screen *sscreen,
struct r600_texture *rtex)
{
si_texture_get_fmask_info(sscreen, rtex,
rtex->buffer.b.b.nr_samples, &rtex->fmask);
rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
rtex->size = rtex->fmask.offset + rtex->fmask.size;
@@ -1046,22 +1046,22 @@ void si_print_texture_info(struct si_screen *sscreen,
rtex->surface.u.gfx9.surf_slice_size,
rtex->surface.surf_alignment,
rtex->surface.u.gfx9.surf.swizzle_mode,
rtex->surface.u.gfx9.surf.epitch,
rtex->surface.u.gfx9.surf_pitch);
if (rtex->fmask.size) {
u_log_printf(log, " FMASK: offset=%"PRIu64",
size=%"PRIu64", "
"alignment=%u, swmode=%u, epitch=%u\n",
rtex->fmask.offset,
- rtex->surface.u.gfx9.fmask_size,
- rtex->surface.u.gfx9.fmask_alignment,
+ rtex->surface.fmask_size,
+ rtex->surface.fmask_alignment,
rtex->surface.u.gfx9.fmask.swizzle_mode,
rtex->surface.u.gfx9.fmask.epitch);
}
if (rtex->cmask.size) {
u_log_printf(log, " CMask: offset=%"PRIu64",
size=%"PRIu64", "
"alignment=%u, rb_aligned=%u,
pipe_aligned=%u\n",
rtex->cmask.offset,
rtex->surface.u.gfx9.cmask_size,
rtex->surface.u.gfx9.cmask_alignment,
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index 58114888966..61220ed7fe3 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -270,23 +270,23 @@ static int radeon_winsys_surface_init(struct
radeon_winsys *rws,
}
if (radeon_winsys_surface_init(rws, &templ, fmask_flags, bpe,
RADEON_SURF_MODE_2D, &fmask)) {
fprintf(stderr, "Got error in surface_init while allocating
FMASK.\n");
return -1;
}
assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
- surf_ws->u.legacy.fmask.size = fmask.surf_size;
- surf_ws->u.legacy.fmask.alignment = MAX2(256, fmask.surf_alignment);
- surf_ws->u.legacy.fmask.tile_swizzle = fmask.tile_swizzle;
+ surf_ws->fmask_size = fmask.surf_size;
+ surf_ws->fmask_alignment = MAX2(256, fmask.surf_alignment);
+ surf_ws->fmask_tile_swizzle = fmask.tile_swizzle;
surf_ws->u.legacy.fmask.slice_tile_max =
(fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y)
/ 64;
if (surf_ws->u.legacy.fmask.slice_tile_max)
surf_ws->u.legacy.fmask.slice_tile_max -= 1;
surf_ws->u.legacy.fmask.tiling_index = fmask.u.legacy.tiling_index[0];
surf_ws->u.legacy.fmask.bankh = fmask.u.legacy.bankh;
surf_ws->u.legacy.fmask.pitch_in_pixels =
fmask.u.legacy.level[0].nblk_x;
}
--
2.17.0
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