On 2018-04-04 03:59 AM, Marek Olšák wrote:
> From: Marek Olšák <marek.ol...@amd.com>
>
> This enables the tile swizzle for some cases of the displayable micro mode,
> and it also fixes an addrlib assertion failure on Vega.
> ---
> src/amd/common/ac_surface.c | 18 ++++++++++++++----
> 1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
> index b294cd85259..2b20a553d51 100644
> --- a/src/amd/common/ac_surface.c
> +++ b/src/amd/common/ac_surface.c
> @@ -408,20 +408,29 @@ static unsigned cik_get_macro_tile_index(struct
> radeon_surf *surf)
> tileb = 8 * 8 * surf->bpe;
> tileb = MIN2(surf->u.legacy.tile_split, tileb);
>
> for (index = 0; tileb > 64; index++)
> tileb >>= 1;
>
> assert(index < 16);
> return index;
> }
>
> +static bool get_display_flag(const struct ac_surf_config *config,
> + const struct radeon_surf *surf)
> +{
> + return surf->flags & RADEON_SURF_SCANOUT &&
> + !(surf->flags & RADEON_SURF_FMASK) &&
> + config->info.samples <= 1 &&
> + surf->bpe >= 4 && surf->bpe <= 8;
surf->bpe is the number of bytes used to store each pixel, right? If so,
this cannot exclude surf->bpe < 4, since 16 bpp and 8 bpp formats can be
displayed.
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X developer
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