From: Marek Olšák <marek.ol...@amd.com>
---
src/amd/common/ac_surface.c | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 1e1641daeec..b294cd85259 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -807,21 +807,22 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
surf->is_displayable = surf->is_linear ||
surf->micro_tile_mode ==
RADEON_MICRO_MODE_DISPLAY ||
surf->micro_tile_mode ==
RADEON_MICRO_MODE_ROTATED;
return 0;
}
/* This is only called when expecting a tiled layout. */
static int
gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
- bool is_fmask, AddrSwizzleMode *swizzle_mode)
+ bool is_fmask, unsigned flags,
+ AddrSwizzleMode *swizzle_mode)
{
ADDR_E_RETURNCODE ret;
ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
sin.flags = in->flags;
sin.resourceType = in->resourceType;
@@ -832,20 +833,27 @@ gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle
modes */
sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */
sin.bpp = in->bpp;
sin.width = in->width;
sin.height = in->height;
sin.numSlices = in->numSlices;
sin.numMipLevels = in->numMipLevels;
sin.numSamples = in->numSamples;
sin.numFrags = in->numFrags;
+ if (flags & RADEON_SURF_SCANOUT)
+ sin.preferredSwSet.sw_D = 1;
+ else if (in->flags.depth || in->flags.stencil || is_fmask)
+ sin.preferredSwSet.sw_Z = 1;
+ else
+ sin.preferredSwSet.sw_S = 1;
+
if (is_fmask) {
sin.flags.color = 0;
sin.flags.fmask = 1;
}
ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
if (ret != ADDR_OK)
return ret;
*swizzle_mode = sout.swizzleMode;
@@ -1029,21 +1037,23 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
}
/* FMASK */
if (in->numSamples > 1) {
ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
- ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
true, &fin.swizzleMode);
+ ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
+ true, surf->flags,
+ &fin.swizzleMode);
if (ret != ADDR_OK)
return ret;
fin.unalignedWidth = in->width;
fin.unalignedHeight = in->height;
fin.numSlices = in->numSlices;
fin.numSamples = in->numSamples;
fin.numFrags = in->numFrags;
ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
@@ -1225,21 +1235,22 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
break;
case RADEON_SURF_MODE_1D:
case RADEON_SURF_MODE_2D:
if (surf->flags & RADEON_SURF_IMPORTED) {
AddrSurfInfoIn.swizzleMode =
surf->u.gfx9.surf.swizzle_mode;
break;
}
- r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
false,
+ r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
+ false, surf->flags,
&AddrSurfInfoIn.swizzleMode);
if (r)
return r;
break;
default:
assert(0);
}
surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
@@ -1261,21 +1272,22 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
if (r)
return r;
/* Calculate texture layout information for stencil. */
if (surf->flags & RADEON_SURF_SBUFFER) {
AddrSurfInfoIn.flags.stencil = 1;
AddrSurfInfoIn.bpp = 8;
AddrSurfInfoIn.format = ADDR_FMT_8;
if (!AddrSurfInfoIn.flags.depth) {
- r = gfx9_get_preferred_swizzle_mode(addrlib,
&AddrSurfInfoIn, false,
+ r = gfx9_get_preferred_swizzle_mode(addrlib,
&AddrSurfInfoIn,
+ false, surf->flags,
&AddrSurfInfoIn.swizzleMode);
if (r)
return r;
} else
AddrSurfInfoIn.flags.depth = 0;
r = gfx9_compute_miptree(addrlib, config, surf, compressed,
&AddrSurfInfoIn);
if (r)
return r;
--
2.15.1
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