From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeon/r600_texture.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index 55670945b90..8d4d771155a 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1434,20 +1434,27 @@ r600_choose_tiling(struct si_screen *sscreen,
}
struct pipe_resource *si_texture_create(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
struct si_screen *sscreen = (struct si_screen*)screen;
struct radeon_surf surface = {0};
bool is_flushed_depth = templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH;
bool tc_compatible_htile =
sscreen->info.chip_class >= VI &&
+ /* There are issues with TC-compatible HTILE on Tonga (and
+ * Iceland is the same design), and documented bug workarounds
+ * don't help. For example, this fails:
+ * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow
-auto
+ */
+ sscreen->info.family != CHIP_TONGA &&
+ sscreen->info.family != CHIP_ICELAND &&
(templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY) &&
!(sscreen->debug_flags & DBG(NO_HYPERZ)) &&
!is_flushed_depth &&
templ->nr_samples <= 1 && /* TC-compat HTILE is less efficient
with MSAA */
util_format_is_depth_or_stencil(templ->format);
int r;
r = r600_init_surface(sscreen, &surface, templ,
r600_choose_tiling(sscreen, templ,
tc_compatible_htile),
--
2.15.1
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