From: Marek Olšák <marek.ol...@amd.com>
just pass the flag that indicates it.
---
src/gallium/drivers/radeon/r600_texture.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index ae9623a829d..55670945b90 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -31,21 +31,21 @@
#include "util/u_resource.h"
#include "util/u_surface.h"
#include "util/os_time.h"
#include <errno.h>
#include <inttypes.h>
#include "state_tracker/drm_driver.h"
#include "amd/common/sid.h"
static enum radeon_surf_mode
r600_choose_tiling(struct si_screen *sscreen,
- const struct pipe_resource *templ);
+ const struct pipe_resource *templ, bool tc_compatible_htile);
bool si_prepare_for_dma_blit(struct r600_common_context *rctx,
struct r600_texture *rdst,
unsigned dst_level, unsigned dstx,
unsigned dsty, unsigned dstz,
struct r600_texture *rsrc,
unsigned src_level,
const struct pipe_box *src_box)
{
@@ -502,21 +502,21 @@ static void r600_reallocate_texture_inplace(struct
r600_common_context *rctx,
templ.bind |= new_bind_flag;
if (rtex->resource.b.is_shared)
return;
if (new_bind_flag == PIPE_BIND_LINEAR) {
if (rtex->surface.is_linear)
return;
/* This fails with MSAA, depth, and compressed textures. */
- if (r600_choose_tiling(rctx->screen, &templ) !=
+ if (r600_choose_tiling(rctx->screen, &templ, false) !=
RADEON_SURF_MODE_LINEAR_ALIGNED)
return;
}
new_tex = (struct r600_texture*)screen->resource_create(screen, &templ);
if (!new_tex)
return;
/* Copy the pixels to the new texture. */
if (!invalidate_storage) {
@@ -1361,41 +1361,39 @@ r600_texture_create_object(struct pipe_screen *screen,
u_log_new_page_print(&log, stdout);
fflush(stdout);
u_log_context_destroy(&log);
}
return rtex;
}
static enum radeon_surf_mode
r600_choose_tiling(struct si_screen *sscreen,
- const struct pipe_resource *templ)
+ const struct pipe_resource *templ, bool tc_compatible_htile)
{
const struct util_format_description *desc =
util_format_description(templ->format);
bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format)
&&
!(templ->flags &
R600_RESOURCE_FLAG_FLUSHED_DEPTH);
/* MSAA resources must be 2D tiled. */
if (templ->nr_samples > 1)
return RADEON_SURF_MODE_2D;
/* Transfer resources should be linear. */
if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
return RADEON_SURF_MODE_LINEAR_ALIGNED;
/* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
* which requires 2D tiling.
*/
- if (sscreen->info.chip_class == VI &&
- is_depth_stencil &&
- (templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY))
+ if (sscreen->info.chip_class == VI && tc_compatible_htile)
return RADEON_SURF_MODE_2D;
/* Handle common candidates for the linear mode.
* Compressed textures and DB surfaces must always be tiled.
*/
if (!force_tiling &&
!is_depth_stencil &&
!util_format_is_compressed(templ->format)) {
if (sscreen->debug_flags & DBG(NO_TILING))
return RADEON_SURF_MODE_LINEAR_ALIGNED;
@@ -1445,22 +1443,22 @@ struct pipe_resource *si_texture_create(struct
pipe_screen *screen,
sscreen->info.chip_class >= VI &&
(templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY) &&
!(sscreen->debug_flags & DBG(NO_HYPERZ)) &&
!is_flushed_depth &&
templ->nr_samples <= 1 && /* TC-compat HTILE is less efficient
with MSAA */
util_format_is_depth_or_stencil(templ->format);
int r;
r = r600_init_surface(sscreen, &surface, templ,
- r600_choose_tiling(sscreen, templ), 0, 0,
- false, false, is_flushed_depth,
+ r600_choose_tiling(sscreen, templ,
tc_compatible_htile),
+ 0, 0, false, false, is_flushed_depth,
tc_compatible_htile);
if (r) {
return NULL;
}
return (struct pipe_resource *)
r600_texture_create_object(screen, templ, NULL, &surface);
}
static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
