From: Dave Airlie <airl...@redhat.com>
---
src/gallium/drivers/r600/evergreen_compute.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index 7df1c55..b8e1c20 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -701,6 +701,8 @@ static void compute_emit_cs(struct r600_context *rctx,
struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
bool compute_dirty = false;
struct r600_pipe_shader *current;
+ struct r600_shader_atomic combined_atomics[8];
+ uint8_t atomic_used_mask;
/* make sure that the gfx ring is only one active */
if (radeon_emitted(rctx->b.dma.cs, 0)) {
@@ -716,6 +718,11 @@ static void compute_emit_cs(struct r600_context *rctx,
r600_context_add_resource_size(&rctx->b.b, (struct
pipe_resource *)current->bo);
r600_set_atom_dirty(rctx, &rctx->cs_shader_state.atom,
true);
}
+
+ if (evergreen_emit_atomic_buffer_setup(rctx, current,
combined_atomics, &atomic_used_mask)) {
+ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+ radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH)
| EVENT_INDEX(4));
+ }
}
/* Initialize all the compute-related registers.
@@ -770,6 +777,8 @@ static void compute_emit_cs(struct r600_context *rctx,
/* Emit dispatch state and dispatch packet */
evergreen_emit_dispatch(rctx, info);
+ if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI)
+ evergreen_emit_atomic_buffer_save(rctx, true, combined_atomics,
&atomic_used_mask);
/* XXX evergreen_flush_emit() hardcodes the CP_COHER_SIZE to 0xffffffff
*/
rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE |
--
2.9.5
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