Valentine Barshak wrote:
According to the AMCC 440EPX/GRX user manual,
the Chip Select width is always fixed at 1 bit no matter
what is actually read from register DDR_10.
Well, from my point of view original kernel code is correct in this part.
Adding one bit into memory address means multiplying memory size by 2
i.e. cs=2. The question is: is Chip Select bit used in memory address.
ChipSelect input of memory chip enables or disabled it, so if we have
only one BankSel installed/connected (DDR0_10[22:23] is 01 or 10)
there's no need to use Chip Select bit in an address. On the contrary,
if both BankSel lines are connected (DDR0_10[22:23] is 11), to let
memory controller know which memory rank to use, Chip Select bit is
added into memory address. (and yes, if DDR0_10[22:23] is 00 - no ranks
installed, memory size is 0, cs=0)
Original kernel code use exactly the same logic as I described above.
Please suggest if it's wrong.
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