I was just going to submit a patch for that too.
Indeed, the denali_fixup_memsize() miscalculated a couple of address
field widths. We were lucky to eventually get the right result,
because the effect of the first error was killed by the other one.
According to the AMCC 440EPX/GRX user manual,
the Chip Select width is always fixed at 1 bit no matter
what is actually read from register DDR_10.
The workaround is to use a predefined chipselect value for 440EPx/GRx.
Also, setting the REDUC bit (REDUC = 1) enables 32-bit data path.
If REDUC = 0, full data path of 64 bits is used.
Signed-off-by: Valentine Barshak <vbars...@ru.mvista.com>
Signed-off-by: Mikhail Zolotaryov <le...@lebon.org.ua>
--- a/arch/powerpc/boot/4xx.c 2008-04-26 02:18:34.000000000 +0400
+++ b/arch/powerpc/boot/4xx.c 2008-10-26 01:40:27.000000000 +0400
@@ -173,15 +173,20 @@ void ibm4xx_denali_fixup_memsize(void)
max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT);
max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
- /* get CS value */
- val = SDRAM0_READ(DDR0_10);
-
- val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
- cs = 0;
- while (val) {
- if (val & 0x1)
- cs++;
- val = val >> 1;
+ /* 440EPx/GRx chipselect always fixed at 1 bit */
+ if ((mfpvr() & 0xf0000ff0) == 0x200008D0)
+ cs = 1;
+ else {
+ /* get CS value */
+ val = SDRAM0_READ(DDR0_10);
+ val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
+
+ cs = 0;
+ while (val) {
+ if (val & 0x1)
+ cs++;
+ val = val >> 1;
+ }
}
if (!cs)
@@ -192,7 +197,7 @@ void ibm4xx_denali_fixup_memsize(void)
/* get data path bytes */
val = SDRAM0_READ(DDR0_14);
- if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
+ if (!DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
dpath = 8; /* 64 bits */
else
dpath = 4; /* 32 bits */
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