Timur Tabi wrote:
Scott Wood wrote:
That's implementation dependent, and support for accesses to uncached
memory is being phased out of book E according to the E500 manual.
What's wrong with uncached memory?
The typical implementation of lwarx/stwcx depends on holding the
reserved cache line in exclusive state, and stwcx failing if it is no
longer exclusive.
I figured that if I could use lwarx/stwcx to make clrsetbits atomic, there would
be no need to spinlocks protecting an individual register.
OK, so you're not trying to be atomic with respect to the device, just
with respect to other cores? Just use the spinlock.
-Scott
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