Scott Wood wrote: > That's implementation dependent, and support for accesses to uncached > memory is being phased out of book E according to the E500 manual.
What's wrong with uncached memory? >> The reservation is held within the processor, so it should work on I/O. > > Even if the core supports lwarx/stwcx to uncached memory, the I/O bus > must support atomic read-modify-write transactions for this to work. Why? I thought the way that lwarx/stwcx work is that since the processor detects the reservation collision, and the processor is one doing the writes, that it would know when the reservation collided. Why does the I/O bus need to know anything? > Why do you think you need lwarx/stwcx to I/O? I figured that if I could use lwarx/stwcx to make clrsetbits atomic, there would be no need to spinlocks protecting an individual register. -- Timur Tabi Linux kernel developer at Freescale _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
