On Sat, Mar 31, 2012 at 11:21:59AM +0200, Daniel Vetter wrote: > Bspec says that we need to set this: vol1c.3 "Blitter Command > Streamer", Section 1.1.2.1 "GAB_CTL_REG - GAB Unit Control Register". > > We don't really rely on pagefaults, but who knows what this all > affects. > > Signed-Off-by: Daniel Vetter <daniel.vet...@ffwll.ch> Reviewed-by: Ben Widawsky <b...@bwidawsk.net> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
- [Intel-gfx] [PATCH 2/7] drm/i915: implement a media hang w/a Daniel Vetter
- [Intel-gfx] [PATCH 3/7] drm/i915: set w/a bit for snb pagefa... Daniel Vetter
- Re: [Intel-gfx] [PATCH 3/7] drm/i915: set w/a bit for s... Ben Widawsky
- [Intel-gfx] [PATCH 4/7] drm/i915: properly set ppgtt cacheab... Daniel Vetter
- Re: [Intel-gfx] [PATCH 4/7] drm/i915: properly set ppgt... Ben Widawsky
- Re: [Intel-gfx] [PATCH 4/7] drm/i915: properly set ... Daniel Vetter
- Re: [Intel-gfx] [PATCH 4/7] drm/i915: properly ... Ben Widawsky
- [Intel-gfx] [PATCH 5/7] drm/i915: implement w/a for incorrec... Daniel Vetter
- Re: [Intel-gfx] [PATCH 5/7] drm/i915: implement w/a for... Ben Widawsky
- Re: [Intel-gfx] [PATCH 5/7] drm/i915: implement w/a... Daniel Vetter
- [Intel-gfx] [PATCH 6/7] drm/i915: implement async flush w/a Daniel Vetter