On Sat, Mar 31, 2012 at 11:21:57AM +0200, Daniel Vetter wrote: > According to an internal workaround master list, we need to set bit 5 > of register 9400 to avoid issues with color blits. > > Signed-Off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
I'm having a lot of trouble actually tracking this one down in something other than the magical spreadsheet. So I'll for now, this is only Acked-by: Ben Widawsky <b...@bwidawsk.net> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
