On Sat, Mar 31, 2012 at 11:22:01AM +0200, Daniel Vetter wrote: > According to Bsepc, this should be set by default, but isn't. See vo1c.4 > "Render Engine Command Streamer", Section 1.1.14.3 "3D_CHICKEN3" > > Bspec also says that we always need to set all mask bits. I think this deserves to be a comment in the code itself. That really made me say WTF when looking at the patch. > > Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch> Reviewed-by: Ben Widawsky <b...@bwidawsk.net> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
- [Intel-gfx] [PATCH 2/7] drm/i915: implement a media hang w/a Daniel Vetter
- [Intel-gfx] [PATCH 3/7] drm/i915: set w/a bit for snb pagefa... Daniel Vetter
- [Intel-gfx] [PATCH 4/7] drm/i915: properly set ppgtt cacheab... Daniel Vetter
- Re: [Intel-gfx] [PATCH 4/7] drm/i915: properly set ppgt... Ben Widawsky
- Re: [Intel-gfx] [PATCH 4/7] drm/i915: properly set ... Daniel Vetter
- [Intel-gfx] [PATCH 5/7] drm/i915: implement w/a for incorrec... Daniel Vetter
- Re: [Intel-gfx] [PATCH 5/7] drm/i915: implement w/a for... Ben Widawsky
- Re: [Intel-gfx] [PATCH 5/7] drm/i915: implement w/a... Daniel Vetter
- [Intel-gfx] [PATCH 6/7] drm/i915: implement async flush w/a Daniel Vetter
- [Intel-gfx] [PATCH 7/7] drm/i915: set stc evict disable lra ... Daniel Vetter