Am Samstag, den 31.03.2012, 11:21 +0200 schrieb Daniel Vetter: > According to an internal workaround master list, we need to set bit 5 > of register 9400 to avoid issues with color blits. > > Signed-Off-by: Daniel Vetter <daniel.vet...@ffwll.ch> > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_display.c | 4 ++++ > 2 files changed, 7 insertions(+), 0 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 3886cf0..233dbd5 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3727,6 +3727,9 @@ > #define GT_FIFO_FREE_ENTRIES 0x120008 > #define GT_FIFO_NUM_RESERVED_ENTRIES 20 > > +#define GEN6_UCGCTL1 0x9400 > +# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) > + > #define GEN6_UCGCTL2 0x9404 > # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) > # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index d514719..aa0c6df 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -8510,6 +8510,10 @@ static void gen6_init_clock_gating(struct drm_device > *dev) > I915_WRITE(WM2_LP_ILK, 0); > I915_WRITE(WM1_LP_ILK, 0); > > + I915_WRITE(GEN6_UCGCTL1, > + I915_READ(GEN6_UCGCTL1) | > + GEN6_BLBUNIT_CLOCK_GATE_DISABLE); > +
Should a comment be added to the header file or here that this is from an internal workaround list? (Same for patch 7/7 I think.) > /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock > * gating disable must be set. Failure to set it results in > * flickering pixels due to Z write ordering failures after Thanks, Paul
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