On Thu, 15 Jan 2015 13:49:16 -0600, John McKown wrote: >5) SMT (hyperthreading) only on IFL and zIIP engines (not CPs). Apparently >when running SMT, the individual threads can't match the speed of a non-SMT >CP, but their aggregate power may.
I think of it this way. Remember in the old days when we ran uniprocessors. Every time one job accessed DASD, it had to wait for the I/O operation to complete. During that time, the operating system let another job run. Today's processors have cache because main memory is _really_ slow compared to the processor. When the processor accesses something at a memory address, if the data at that location is in the cache, the processor can access it in one clock cycle (if it is in the on-chip cache) or a few clock cycles if it is farther away. If it is not in cache and the processor has to get the data from memory, it takes hundreds of cycles. During that "wait" time, the processor will switch to another thread to execute. Now that thread will run until it has to access main memory, and the processor will switch again. In this way, at least some of the time that the processor is idle waiting for data from memory, it is able to do useful work. -- Tom Marchant ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
