On Fri, Jan 16, 2015 at 9:38 AM, David Crayford <[email protected]> wrote:

> On 16/01/2015 11:16 PM, John McKown wrote:
>
>> On Fri, Jan 16, 2015 at 8:24 AM, Bob Shannon <[email protected]
>> >
>> wrote:
>>
>>  So, as an extremely silly example. SMT will not "help" in the following
>>>>
>>> program: I.e. in a "hard loop" which uses data & instructions
>>>
>>> There are exceptions to every rule. If that’s the type of workload you
>>> run, turn SMT off.
>>>
>>> Bob Shannon
>>> Rocket Software
>>>
>>>  ​Basically, I'm trying to conceptualize how z SMT compares to Intel's.
>>
>
> Better to compare it to the POWER arch http://www-03.ibm.com/systems/
> resources/pwrsysperf_SMT4OnP7.pdf.
> It may be CISC not RISC but those lines are getting more blured with every
> new churn of z. I would imagine that the
> SIMD vector units also originate  from POWER. It may seem far fetched but
> I can see a time in the not too distant future
> when the two architectures are converged.
>

​I said something similar to that on the IBMVM forum. Alan Altmark (alter
ego: "Chuckie") of IBM, but not speaking for IBM, said that _he_ did not
think this was likely.​ I was envisioning a single CEC running the z, i,
and p software in different hardware partitions. But given the zBX and some
"fundamental internal architecture differences" between the z and p chips,
I guess this is unlikely. Unless IBM makes a z/PDT type "dongle" and an
instruction emulator for the Power platform. Again, unlikely.



>
>
>>
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-- 
​
While a transcendent vocabulary is laudable, one must be eternally careful
so that the calculated objective of communication does not become ensconced
in obscurity.  In other words, eschew obfuscation.

111,111,111 x 111,111,111 = 12,345,678,987,654,321

Maranatha! <><
John McKown

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