Joe Buck wrote:
On Thu, Jun 19, 2008 at 03:50:34PM -0500, Joel Sherrill wrote:
On Thu, Jun 19, 2008 at 1:36 PM, Joel Sherrill
<[EMAIL PROTECTED]> wrote:
Hi,
I ran into something tracking down a test
failure on psim and now thing there is a
target specific issue that needs addressing.
Andrew Pinski wrote:
lwsync is sync with the bit 9 set. So it should be ok as it was a
reserved field and was supposed to be ignored on the hardware which
did not implement those bits and have it as a sync (but I could be
wrong).
Based on
http://gcc.gnu.org/ml/gcc-patches/2006-11/msg01238.html
it appears that it is not ignored, but rather traps, on at least some
hardware. As a rule (thanks to some bad experiences with the Motorola
68000) processor architects tend to make sure that reserved bits and
unused bits generate a trap, otherwise the software developers start using
those bits for some other purpose and constrain future processor
development.
I agree completely and my 13 year old 603e manual shows
bit 9 as reserved and 0. So using your argument,
gcc should not generate an lwsync for 603e.
Is the set of CPU models gcc can generate an lwsync for
to generous?
I really don't know what to make of this now. Should
gcc not generate lwsync for a 603e and psim is right
Or should psim be fixed to allow bit 9 to be set?
If psim's going to support both older and newer processors,
simulated, it appears it has to depend on the specific processor
being simulated (so psim should make both behaviors possible).
Yep. But I don't see anything too new in the
set of 601, 603, 603e and 604. :-D
--
Joel Sherrill, Ph.D. Director of Research & Development
[EMAIL PROTECTED] On-Line Applications Research
Ask me about RTEMS: a free RTOS Huntsville AL 35805
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