Andrew Pinski wrote:
On Thu, Jun 19, 2008 at 1:36 PM, Joel Sherrill
<[EMAIL PROTECTED]> wrote:
Hi,
I ran into something tracking down a test
failure on psim and now thing there is a
target specific issue that needs addressing.
lwsync is sync with the bit 9 set. So it should be ok as it was a
reserved field and was supposed to be ignored on the hardware which
did not implement those bits and have it as a sync (but I could be
wrong).
I don't have access to a real 603e of this vintage but
my Sept 1995 603e User's Manual shows the sync
instruction has having:
0-5 - all 1's (value in table is 31)
6-20 - all 0's (dark grey indicating not implemented)
21-30 - 598
31 - 0
So bit 9 being 1 could be ignored or it could cause
a bad instruction fault. psim makes it a fault.
The Power ISA 2.05 describes the sync/lwsync behavior but I can't find
where it says it is ignored if not implemented. I bet you have to
goto the ISA for those processors to find what is the current behavior
for sure.
My 1994 copy of "PowerPC Microprocessor Architecture:
The Programming Environment" shows the bits that are
0 in the 603e manual as reserved.
I really don't know what to make of this now. Should
gcc not generate lwsync for a 603e and psim is right
Or should psim be fixed to allow bit 9 to be set?
And if psim should be fixed, can you explain how to change
this? I have never been able to grok this format and this
seems like the simplest possible change. :D
0.31,6./,11./,16./,21.598,31./:X::sync:Synchronize
*601: PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*603: PPC_UNIT_SRU, PPC_UNIT_SRU, 1, 1, 0
*603e:PPC_UNIT_SRU, PPC_UNIT_SRU, 1, 1, 0
*604: PPC_UNIT_LSU, PPC_UNIT_LSU, 1, 1, 0
/* do nothing */
What do you have to do to that first line to say the value
of bit 9 doesn't matter? And where is this explained
in the code? :-D
I can scan the pages and email them to you if you like.
Thanks,
Andrew Pinski
--
Joel Sherrill, Ph.D. Director of Research & Development
[EMAIL PROTECTED] On-Line Applications Research
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