On Saturday 26 March 2005 04:11, Ian Lance Taylor wrote: > I'm also not aware of processors changing as you describe,
Well, ia64 comes to mind. Take the cmp4.* instructions for example. They are of the form "(predicate) cmp4.cmpoperator p1,p2 = cmpoperands" where p1 and p2 are predicate registers that are both set to something depending on the result of the comparison. Guessing and hand waving starts here... ;-) As far as I can tell, there is no architecture requirement that p1 and p2 must be a register pair (ie. p6,p7 or p2,p3, etc.), but that seems to be the only form that GCC can produce. All cmp4 patterns in ia64.md have a single set to p1, and an assembler output template of the form "cmp4.* %0, %I0 = %3, %2" where the I means "Invert a predicate register by adding 1". Perhaps this was done this way to avoid insn patterns with two sets? Gr. Steven
