Hi Ian, (getting back to reality) upon reviewing things further, it appears
that if GCC could relax it's single-set restriction to enable a restricted
form of multi-set instructions to be included in optimizations; then ISA's
who's instructions either implicitly set or depend on global machine state
which directly correspond to that instruction's single result value, would
be enabled to be both accurately modeled and fully safely optimized.
More specifically, if GCC enabled set to optionally specify multiple targets
for a single rtl source expression, i.e.:
(set ((reg:xx %0) (reg CC) ...) (some-expression:xx ...))
Then it would seem that this single common rtl source expression may be
optimized as if it were a single-set expression with the only restriction
that instructions with multiple active sets may only be merged with it's
source operand instructions when all of it's live sets may correspondingly
be represented in the newly merged instruction, i.e.:
(add %0 %1); (set ((reg %0) (reg CC)) (add (reg %0) (reg %1))
; %0 live, CC dead
(sub %0 1) ; (set ((reg %0) (reg CC)) (sub (reg %0) (int 1))
; %0 live, CC live
=>
(add-1 a b); (set ((reg %0) (reg CC)) (sub (add (reg %0) (reg %1)) (int 1)))
; %0 live, CC live
Thereby enabling clean fully exposed global-cc-status target descriptions:
(insn xxxx (set ((reg %0) (reg CC)) (xxxx (reg: %0) (reg: %1)))
...)
(insn brne (set (PC) (if_then_else
(ne: 0 (reg CC))
(label_ref %0)
(PC))))
...)
Might this likely work? And if so, possibly be worthy of consideration to
enable the more efficient description and optimization of traditional cc0
target machines (and possibly be beneficial for other ISA's as well)?
