The ARMv8.1 architecture extension adds two Adv.SIMD instructions,
sqrdmlah and sqrdmlsh. This patch adds the GCC builtins to generate the new
instructions which are needed for the NEON intrinsics added later in
this series.
Tested the series for aarch64-none-linux-gnu with native bootstrap and
make check on an ARMv8 architecture. Also tested aarch64-none-elf with
cross-compiled check-gcc on an ARMv8.1 emulator.
Ok for trunk?
Matthew
gcc/
2015-10-23 Matthew Wahab <matthew.wa...@arm.com>
* config/aarch64/aarch64-simd-builtins.def
(sqrdmlah, sqrdmlsh): New.
(sqrdmlah_lane, sqrdmlsh_lane): New.
(sqrdmlah_laneq, sqrdmlsh_laneq): New.
>From b4a480cf0e38caa156b2fa15fc30b12ab8e0e7ad Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wa...@arm.com>
Date: Thu, 27 Aug 2015 13:15:34 +0100
Subject: [PATCH 3/7] Add builtins for RDMA instructions.
Change-Id: I5156884010b1f6171583229c816aef4daab23b8f
---
gcc/config/aarch64/aarch64-simd-builtins.def | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 654e963..4cc4559 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -412,3 +412,17 @@
/* Implemented by aarch64_tbx4v8qi. */
VAR1 (TERNOP, tbx4, 0, v8qi)
+
+ /* Builtins for ARMv8.1 Adv.SIMD instructions. */
+
+ /* Implemented by aarch64_sqrdml<SQRDMLAH:rdma_as>h<mode>. */
+ BUILTIN_VSDQ_HSI (TERNOP, sqrdmlah, 0)
+ BUILTIN_VSDQ_HSI (TERNOP, sqrdmlsh, 0)
+
+ /* Implemented by aarch64_sqrdml<SQRDMLAH:rdma_as>h_lane<mode>. */
+ BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_lane, 0)
+ BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_lane, 0)
+
+ /* Implemented by aarch64_sqrdml<SQRDMLAH:rdma_as>h_laneq<mode>. */
+ BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_laneq, 0)
+ BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0)
--
2.1.4
