The ARMv8.1 architecture extension adds two Adv.SIMD instructions,
sqrdmlah and sqrdmlsh. This patch adds the instructions to the
aarch64-simd patterns, making them conditional on the TARGET_SIMD_RDMA
feature macro introduced in the previous patch.
The instructions patterns are defined using unspec expressions, so that
they are only generated through builtins added by this patch series. To
simplify the definition, iterators SQRDMLAH and rdma_as are added, to
iterate over the add (sqrdmlah) and subtract (sqrdmlsh) forms of the
instructions.
Tested the series for aarch64-none-linux-gnu with native bootstrap and
make check on an ARMv8 architecture. Also tested aarch64-none-elf with
cross-compiled check-gcc on an ARMv8.1 emulator.
Ok for trunk?
Matthew
gcc/
2015-10-23 Matthew Wahab <matthew.wa...@arm.com>
* config/aarch64/aarch64-simd.md
(aarch64_sqmovun<mode>): Fix some white-space.
(aarch64_<sur>qmovun<mode>): Likewise.
(aarch64_sqrdml<SQRDMLAH:rdma_as>h<mode>): New.
(aarch64_sqrdml<SQRDMLAH:rdma_as>h_lane<mode>): New.
(aarch64_sqrdml<SQRDMLAH:rdma_as>h_laneq<mode>): New.
* config/aarch64/iterators.md (UNSPEC_SQRDMLAH): New.
(UNSPEC_SQRDMLSH): New.
(SQRDMLAH): New.
(rdma_as): New.
>From 3505963108eac78ad5e224a0e558cce82ac8e127 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wa...@arm.com>
Date: Mon, 7 Sep 2015 18:57:37 +0100
Subject: [PATCH 2/7] Add RDMA simd instruction patterns.
Change-Id: I87043d052c660b7ce9b6d881293abe880efb795e
---
gcc/config/aarch64/aarch64-simd.md | 94 +++++++++++++++++++++++++++++++++++++-
gcc/config/aarch64/iterators.md | 6 +++
2 files changed, 98 insertions(+), 2 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 167277e..cf87ac2 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -2852,7 +2852,7 @@
"TARGET_SIMD"
"sqxtun\\t%<vn2>0<Vmntype>, %<v>1<Vmtype>"
[(set_attr "type" "neon_sat_shift_imm_narrow_q")]
- )
+)
;; sqmovn and uqmovn
@@ -2863,7 +2863,7 @@
"TARGET_SIMD"
"<sur>qxtn\\t%<vn2>0<Vmntype>, %<v>1<Vmtype>"
[(set_attr "type" "neon_sat_shift_imm_narrow_q")]
- )
+)
;; <su>q<absneg>
@@ -2951,6 +2951,96 @@
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
)
+;; sqrdml[as]h.
+
+(define_insn "aarch64_sqrdml<SQRDMLAH:rdma_as>h<mode>"
+ [(set (match_operand:VSDQ_HSI 0 "register_operand" "=w")
+ (unspec:VSDQ_HSI
+ [(match_operand:VSDQ_HSI 1 "register_operand" "0")
+ (match_operand:VSDQ_HSI 2 "register_operand" "w")
+ (match_operand:VSDQ_HSI 3 "register_operand" "w")]
+ SQRDMLAH))]
+ "TARGET_SIMD_RDMA"
+ "sqrdml<SQRDMLAH:rdma_as>h\\t%<v>0<Vmtype>, %<v>2<Vmtype>, %<v>3<Vmtype>"
+ [(set_attr "type" "neon_sat_mla_<Vetype>_long")]
+)
+
+;; sqrdml[as]h_lane.
+
+(define_insn "aarch64_sqrdml<SQRDMLAH:rdma_as>h_lane<mode>"
+ [(set (match_operand:VDQHS 0 "register_operand" "=w")
+ (unspec:VDQHS
+ [(match_operand:VDQHS 1 "register_operand" "0")
+ (match_operand:VDQHS 2 "register_operand" "w")
+ (vec_select:<VEL>
+ (match_operand:<VCOND> 3 "register_operand" "w")
+ (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
+ SQRDMLAH))]
+ "TARGET_SIMD_RDMA"
+ {
+ operands[4] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[4])));
+ return
+ "sqrdml<SQRDMLAH:rdma_as>h\\t%0.<Vtype>, %2.<Vtype>, %3.<Vetype>[%4]";
+ }
+ [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
+)
+
+(define_insn "aarch64_sqrdml<SQRDMLAH:rdma_as>h_lane<mode>"
+ [(set (match_operand:SD_HSI 0 "register_operand" "=w")
+ (unspec:SD_HSI
+ [(match_operand:SD_HSI 1 "register_operand" "0")
+ (match_operand:SD_HSI 2 "register_operand" "w")
+ (vec_select:<VEL>
+ (match_operand:<VCOND> 3 "register_operand" "w")
+ (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
+ SQRDMLAH))]
+ "TARGET_SIMD_RDMA"
+ {
+ operands[4] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[4])));
+ return
+ "sqrdml<SQRDMLAH:rdma_as>h\\t%<v>0, %<v>2, %3.<Vetype>[%4]";
+ }
+ [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
+)
+
+;; sqrdml[as]h_laneq.
+
+(define_insn "aarch64_sqrdml<SQRDMLAH:rdma_as>h_laneq<mode>"
+ [(set (match_operand:VDQHS 0 "register_operand" "=w")
+ (unspec:VDQHS
+ [(match_operand:VDQHS 1 "register_operand" "0")
+ (match_operand:VDQHS 2 "register_operand" "w")
+ (vec_select:<VEL>
+ (match_operand:<VCONQ> 3 "register_operand" "w")
+ (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
+ SQRDMLAH))]
+ "TARGET_SIMD_RDMA"
+ {
+ operands[4] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[4])));
+ return
+ "sqrdml<SQRDMLAH:rdma_as>h\\t%0.<Vtype>, %2.<Vtype>, %3.<Vetype>[%4]";
+ }
+ [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
+)
+
+(define_insn "aarch64_sqrdml<SQRDMLAH:rdma_as>h_laneq<mode>"
+ [(set (match_operand:SD_HSI 0 "register_operand" "=w")
+ (unspec:SD_HSI
+ [(match_operand:SD_HSI 1 "register_operand" "0")
+ (match_operand:SD_HSI 2 "register_operand" "w")
+ (vec_select:<VEL>
+ (match_operand:<VCONQ> 3 "register_operand" "w")
+ (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
+ SQRDMLAH))]
+ "TARGET_SIMD_RDMA"
+ {
+ operands[4] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[4])));
+ return
+ "sqrdml<SQRDMLAH:rdma_as>h\\t%<v>0, %<v>2, %3.<v>[%4]";
+ }
+ [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
+)
+
;; vqdml[sa]l
(define_insn "aarch64_sqdml<SBINQOPS:as>l<mode>"
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 964f8f1..409ba7b 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -303,6 +303,8 @@
UNSPEC_PMULL2 ; Used in aarch64-simd.md.
UNSPEC_REV_REGLIST ; Used in aarch64-simd.md.
UNSPEC_VEC_SHR ; Used in aarch64-simd.md.
+ UNSPEC_SQRDMLAH ; Used in aarch64-simd.md.
+ UNSPEC_SQRDMLSH ; Used in aarch64-simd.md.
])
;; -------------------------------------------------------------------
@@ -932,6 +934,8 @@
UNSPEC_SQSHRN UNSPEC_UQSHRN
UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
+(define_int_iterator SQRDMLAH [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH])
+
(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
UNSPEC_TRN1 UNSPEC_TRN2
UNSPEC_UZP1 UNSPEC_UZP2])
@@ -1096,3 +1100,5 @@
(UNSPEC_SHA1M "m")])
(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
+
+(define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])
--
2.1.4
