Hi Folks,
I find this discussion interesting and would like to ask a few questions.
>I FIND THAT THE TWO FPGA IMAGES ARE DIFFERENT.
What do you mean by different? Do they behave different? Or you used a program
to compare the binary data comparison between the 2 and this is what you are
saying here?
Xilinx P&R tool as well as it's resource optimizer and mapper use special
algorithm that creates a random path of data for each run, unless you hard code
your blocks and force the MAP and P&R not to touch the blocks, the result of
the 2 identical compilation will be different.
If there are any clocks in the whole design that is not included in the UCF
file, then the MAP will try to find the best placement for it which in almost
99% of the cases when you start a new compile, is different than the one
created earlier.
Xilinx supports partial re-configuration on some it's devices as it is
described here: http://www.xilinx.com/tools/partial-reconfiguration.htm and
that can help those who want to make sure that the differences between
different version of the code/compiles are minimum, but this is not supported
only by the Virtex family of devices and not the Spartan series.
Just my 2c!
BR,
Farhad
>________________________________
>
>
>HOWEVER, when testing this, by building the same fpga image which is
>downloaded to usr/local/share/uhd/images/ by the Marcus's
>build-gnuradio-script,
>I FIND THAT THE TWO FPGA IMAGES ARE DIFFERENT.
>
>WHAT CAN BE THE REASONS THAT TWO FPGA IMAGES ARE DIFFERENT IF ONE IS USING THE
>SAME MAKEFILE?
>
>
>Output for md5sum:
>--------------------------------------
>root@radio-laptop:/usr/local/share/uhd/images# md5sum usrp2_fpga.bin
>4d47274d3255e5bbca6e68e8f0ee7c74 usrp2_fpga.bin
>
>root@radio-laptop:/home/nemanja/bin/uhd/fpga/usrp2/top/USRP2/build# md5sum
>u2_rev3.bin
>d31cdcc7a1fecb3bc33bc7fbc4db2707 u2_rev3.bin
>--------------------------------------
>
>
>ANYONE WITH SUGGESTIONS, PLEASE REPLY!
>
>
>-Nemanja Trecakov
>
>
>
>
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>
>
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