On Tue, Oct 31, 2023 at 9:55 AM Dhaval Sharma <dha...@rivosinc.com> wrote:
>
> I am posting an update on behalf of Jingyu as he had trouble with posting. 
> CC'ing him here:
> In summary what we have verified so far:
>
> I have verified that instructions/op codes are okay. I have also verified on 
> Qemu that functionally it seems to be calling correct instructions. Ensured 
> with negative test cases that any other op codes do cause exceptions as 
> expected.
> Jingyu was able to verify the CpuFlushCpuDataCache function with this 
> framework (he had to use custom op code based on his soc implementation) on 
> SG2042. There is one issue that he is debugging now which is related to other 
> cache instructions and he will get back with more data. P.S. SG2042 does not 
> implement the exact same CMO opcodes but equivalent ones. So this experiment 
> is just an additional data point that helps verify the framework and not CMO 
> itself.
> In general it sounds like framework flows are alright and as long as 
> instructions do their job as claimed in the spec, it is lower risk.
>
> Guess this is what we have so far. If it makes sense to everyone, we could go 
> ahead with merging with this *feature disabled by default* after Jingyu 
> provides clarity reg failures on SG2042 platform. Otherwise we can wait until 
> newer Si is available where these exact instructions can be tested and then 
> upstreamed.

Thanks!

To be clear, I wasn't NAKing it, I even gave you my Rb. I just think
we should be extra careful sending arch-related changes that haven't
been tested on real HW, because hardware tends to be tricky :)

-- 
Pedro


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