On Sun, Oct 29, 2023 at 2:46 PM Dhaval Sharma <dha...@rivosinc.com> wrote: > > Implement Cache Management Operations (CMO) defined by > RISC-V spec https://github.com/riscv/riscv-CMOs. > > Notes: > 1. CMO only supports block based Operations. Meaning cache > flush/invd/clean Operations are not available for the entire > range. In that case we fallback on fence.i instructions. > 2. Operations are implemented using Opcodes to make them compiler > independent. binutils 2.39+ compilers support CMO instructions. > > Test: > 1. Ensured correct instructions are refelecting in asm
nit: reflecting > 2. Not able to verify actual instruction in HW as Qemu ignores > any actual cache operations. Do you have no way to test this in hardware? Since Rivos is a RISCV vendor and all ;) I don't like inviting the idea of merging CPU architectural changes without actually testing them in something resembling real silicon (i.e QEMU KVM is _fine_, QEMU TCG really isn't). -- Pedro -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110276): https://edk2.groups.io/g/devel/message/110276 Mute This Topic: https://groups.io/mt/102256466/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
