On Sun, Oct 29, 2023 at 08:16:11PM +0530, Dhaval wrote: > Implement Cache Management Operations (CMO) defined by > RISC-V spec https://github.com/riscv/riscv-CMOs. > > Notes: > 1. CMO only supports block based Operations. Meaning cache > flush/invd/clean Operations are not available for the entire > range. In that case we fallback on fence.i instructions. > 2. Operations are implemented using Opcodes to make them compiler > independent. binutils 2.39+ compilers support CMO instructions. > > Test: > 1. Ensured correct instructions are refelecting in asm > 2. Not able to verify actual instruction in HW as Qemu ignores > any actual cache operations. > > Cc: Michael D Kinney <michael.d.kin...@intel.com> > Cc: Liming Gao <gaolim...@byosoft.com.cn> > Cc: Zhiguang Liu <zhiguang....@intel.com> > Cc: Sunil V L <suni...@ventanamicro.com> > Cc: Daniel Schaefer <g...@danielschaefer.me> > Cc: Laszlo Ersek <ler...@redhat.com> > > Signed-off-by: Dhaval Sharma <dha...@rivosinc.com> > Reviewed-by: Laszlo Ersek <ler...@redhat.com> > --- > > Notes: > V7: > - Modify instruction names as per feedback from V6 > - Added RB > V6: > - Implement Cache management instructions in Baselib > > MdePkg/Library/BaseLib/BaseLib.inf | 2 +- > MdePkg/Include/Library/BaseLib.h | 33 > ++++++++++++++++++++ > MdePkg/Include/RiscV64/RiscVasm.inc | 19 > +++++++++++ > MdePkg/Library/BaseLib/RiscV64/{FlushCache.S => RiscVCacheMgmt.S} | 17 > ++++++++++ > 4 files changed, 70 insertions(+), 1 deletion(-) > > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf > b/MdePkg/Library/BaseLib/BaseLib.inf > index 03c7b02e828b..53389389448c 100644 > --- a/MdePkg/Library/BaseLib/BaseLib.inf > +++ b/MdePkg/Library/BaseLib/BaseLib.inf > @@ -400,7 +400,7 @@ [Sources.RISCV64] > RiscV64/RiscVCpuBreakpoint.S | GCC > RiscV64/RiscVCpuPause.S | GCC > RiscV64/RiscVInterrupt.S | GCC > - RiscV64/FlushCache.S | GCC > + RiscV64/RiscVCacheMgmt.S | GCC > RiscV64/CpuScratch.S | GCC > RiscV64/ReadTimer.S | GCC > RiscV64/RiscVMmu.S | GCC > diff --git a/MdePkg/Include/Library/BaseLib.h > b/MdePkg/Include/Library/BaseLib.h > index d4b56a9601da..c42cc165dc82 100644 > --- a/MdePkg/Include/Library/BaseLib.h > +++ b/MdePkg/Include/Library/BaseLib.h > @@ -226,6 +226,39 @@ RiscVInvalidateDataCacheAsmFence ( > VOID > ); > > +/** > + RISC-V flush cache block. Atomically perform a clean operation > + followed by an invalidate operation > + > +**/ > +VOID > +EFIAPI > +RiscVCpuCacheFlushAsmCmo (
NIT: I would keep Asm at the end for these interface names. Otherwise, Reviewed-by: Sunil V L <suni...@ventanamicro.com> Thanks, Sunil -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110307): https://edk2.groups.io/g/devel/message/110307 Mute This Topic: https://groups.io/mt/102256466/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
