On 10/30/23 12:22, Sunil V L wrote:
> On Mon, Oct 30, 2023 at 04:48:18PM +0530, Sunil V L wrote:
>> On Sun, Oct 29, 2023 at 08:16:12PM +0530, Dhaval Sharma wrote:
>>> Use newly defined cache management operations for RISC-V where possible
>>> It builds up on the support added for RISC-V cache management
>>> instructions in BaseLib.
>>> Cc: Michael D Kinney <michael.d.kin...@intel.com>
>>> Cc: Liming Gao <gaolim...@byosoft.com.cn>
>>> Cc: Zhiguang Liu <zhiguang....@intel.com>
>>> Cc: Laszlo Ersek <ler...@redhat.com>
>>>
>>> Signed-off-by: Dhaval Sharma <dha...@rivosinc.com>
>>> Acked-by: Laszlo Ersek <ler...@redhat.com>
>>> ---
>>>
>>> Notes:
>>>     V7:
>>>     - Added PcdLib
>>>     - Restructure DEBUG message based on feedback on V6
>>>     - Make naming consistent to CMO, remove all CBO references
>>>     - Add ASSERT for not supported functions instead of plain debug message
>>>     - Added RB tag
>>>     V6:
>>>     - Utilize cache management instructions if HW supports it
>>>       This patch is part of restructuring on top of v5
>>>
>>>  MdePkg/MdePkg.dec                                                  |   8 +
>>>  MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |   5 +
>>>  MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c                | 168 
>>> +++++++++++++++++---
>>>  MdePkg/MdePkg.uni                                                  |   4 +
>>>  4 files changed, 165 insertions(+), 20 deletions(-)
>>>
>>> diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
>>> index ac54338089e8..fa92673ff633 100644
>>> --- a/MdePkg/MdePkg.dec
>>> +++ b/MdePkg/MdePkg.dec
>>> @@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, 
>>> PcdsPatchableInModule.AARCH64]
>>>    # @Prompt CPU Rng algorithm's GUID.
>>>    
>>> gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x00000037
>>>  
>>> +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]
>>> +  #
>>> +  # Configurability to override RISC-V CPU Features
>>> +  # BIT 0 = Cache Management Operations. This bit is relevant only if
>>> +  # previous stage has feature enabled and user wants to disable it.
>> NIT: I am wondering whether PcdRiscVCpuFeatureDisable is better so that
>> it is explicit.
>>
>>> +  #
>>> +  
>>> gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT64|0x69
>>> +
>> Instead of this, can default value match only those features which are
>> enabled by default for qemu virt machine? That way, I think we can avoid
>> having this PCD defined again in RiscVVirt.
>>
> Sorry, I take back. This is common for all platforms. So, we can't take
> qemu as reference.

yes, and sorry that I'm only seeing your addition now!
Laszlo



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