On Mon, Oct 30, 2023 at 9:38 AM Laszlo Ersek <ler...@redhat.com> wrote: > > On 10/29/23 20:12, Pedro Falcato wrote: > > On Sun, Oct 29, 2023 at 2:46 PM Dhaval Sharma <dha...@rivosinc.com> wrote: > >> > >> Implement Cache Management Operations (CMO) defined by > >> RISC-V spec https://github.com/riscv/riscv-CMOs. > >> > >> Notes: > >> 1. CMO only supports block based Operations. Meaning cache > >> flush/invd/clean Operations are not available for the entire > >> range. In that case we fallback on fence.i instructions. > >> 2. Operations are implemented using Opcodes to make them compiler > >> independent. binutils 2.39+ compilers support CMO instructions. > >> > >> Test: > >> 1. Ensured correct instructions are refelecting in asm > > > > nit: reflecting > > > >> 2. Not able to verify actual instruction in HW as Qemu ignores > >> any actual cache operations. > > > > Do you have no way to test this in hardware? Since Rivos is a RISCV > > vendor and all ;) > > I don't like inviting the idea of merging CPU architectural changes > > without actually testing them in something resembling real silicon > > (i.e QEMU KVM is _fine_, QEMU TCG really isn't). > > > > Hopefully I'm not drawing an incorrect parallel here, but, as I recall > arm64 enablement in 2014, nearly all initial enablement in RHEL occurred > on software emulators (ARM Foundation Model, ARM FVP, then QEMU TCG). > You need to start somewhere. In particular, qemu-system-aarch64 was a > huge step forward (performance-wise) once it *existed*, relative to the > Foundation Model / FVP, even though qemu-system-aarch64 wouldn't emulate > CPU caches (IIRC).
Right. I don't know how faithful those early ARM simulators were, but QEMU TCG is not very faithful and uarch details *can* slip through the cracks. In arm64 it's easy to miss a dsb or a isb if you're not extra careful (or read the ARM ARM wrong). RISCV has a bunch of fun gotchas too. For instance, did you know you need to flush the TLB using sfence.vma even when only mapping a page? This "small" detail results in boot failures on real hardware (such as the visionfive 2), but is completely silent in QEMU TCG. So this is why I would much prefer a test on real silicon. It's hard to prove correctness when all you have is QEMU's spotty simulation (rightfully so, it's not a simulator). -- Pedro -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110322): https://edk2.groups.io/g/devel/message/110322 Mute This Topic: https://groups.io/mt/102256466/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
