On Mon, 13 Jul 2020 at 00:54, Mark Tinka <[email protected]> wrote:
> The general messaging, over the years, has been that ASIC is quick but > not flexible, while NPU is flexible but can get bogged down by added > flexibility in time. The classical view is that packet through ASIC takes constant, invariant time, and packet through NPU takes variant time, depending on how many instructions the NPU needs to perform for this packet. But if that is a strict definition, then we don't really have ASICs outside really cheap switches, as there is some programmability in all new stuff being released. So I'm not sure what the correct definition is. Equally when does a software router become a hardware router? Why is XEON not NPU but Trio is? Are there some objective facts which differentiate CPU from NPU and NPU from ASIC? # NPU vs CPU? - NPU tends to have more cores than CPU - NPU has application specific instruction set - NPU has application specific memory interface # NPU vs ASIC? - ASIC does parsing and lookup in silicon, not by running a set of instruction given by a program - ASIC is constant time, NPU is variable time - ASIC has many type of silicons for different function, NPU has many identical siicons running different set of instruction depending on packet/config -- ++ytti _______________________________________________ cisco-nsp mailing list [email protected] https://puck.nether.net/mailman/listinfo/cisco-nsp archive at http://puck.nether.net/pipermail/cisco-nsp/
