[llvm] [clang] [SME2] Add LUTI2 and LUTI4 quad Builtins and Intrinsics (PR #73317)

[Matthew Devereau via cfe-commits]

================
@@ -1859,6 +1867,34 @@ void AArch64DAGToDAGISel::SelectFrintFromVT(SDNode *N, 
unsigned NumVecs,
   SelectUnaryMultiIntrinsic(N, NumVecs, true, Opcode);
 }
 
+template <int64_t Max>
+void AArch64DAGToDAGISel::SelectMultiVectorLuti(SDNode *Node,
+                                                unsigned NumOutVecs,
+                                                unsigned Opc) {
+  if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Node->getOperand(4)))
+    if (Imm->getZExtValue() > Max)
+      return;
+
+  SDValue ZtValue;
+  ImmToTile<AArch64::ZT0, 0>(Node->getOperand(2), ZtValue);
----------------
MDevereau wrote:

I'm not quite sure what you mean here. Why would `Op2 != 0` crash? I think 
tests added such as [this 
one](https://github.com/llvm/llvm-project/pull/73317/files/32ce28d2fccda24ea9b223f204ca327133e3d0f9#diff-4626c48918de6a8e9ba8eecc9909d7a6febd2208294852599d4b147f6906656fR188-R189)
 should demonstrate Op2 != 0 ok

https://github.com/llvm/llvm-project/pull/73317
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