[clang] [llvm] [SME2] Add LUTI2 and LUTI4 quad Builtins and Intrinsics (PR #73317)

[Matthew Devereau via cfe-commits]

================
@@ -1859,6 +1867,34 @@ void AArch64DAGToDAGISel::SelectFrintFromVT(SDNode *N, 
unsigned NumVecs,
   SelectUnaryMultiIntrinsic(N, NumVecs, true, Opcode);
 }
 
+template <int64_t Max>
----------------
MDevereau wrote:

Done

https://github.com/llvm/llvm-project/pull/73317
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