[llvm] [clang] [SME2] Add LUTI2 and LUTI4 quad Builtins and Intrinsics (PR #73317)

[Matthew Devereau via cfe-commits]

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@@ -5098,6 +5099,12 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
                AArch64::LUTI2_4ZTZI_S}))
         // Second Immediate must be <= 3:
         SelectMultiVectorLuti<3>(Node, 4, Opc);
+      else if (auto Opc = SelectOpcodeFromVT<SelectTypeKind::FP>(
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MDevereau wrote:

Yeah that does seem better. I'm not sure what the implications of letting i1, 
i64 and f64 are though.

https://github.com/llvm/llvm-project/pull/73317
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