[llvm] [clang] [SME2] Add LUTI2 and LUTI4 quad Builtins and Intrinsics (PR #73317)

[Kerry McLaughlin via cfe-commits]

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@@ -5098,6 +5099,12 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
                AArch64::LUTI2_4ZTZI_S}))
         // Second Immediate must be <= 3:
         SelectMultiVectorLuti<3>(Node, 4, Opc);
+      else if (auto Opc = SelectOpcodeFromVT<SelectTypeKind::FP>(
----------------
kmclaughlin-arm wrote:

If AnyType is used and i1 is passed, `SelectOpcodeFromVT` will return 0.
I think it would be the same for i64/f64 as the size of `Opcodes` for these 
intrinsics is 3 and the function will check this when trying to return the 
correct opcode from the list:

`return (Opcodes.size() <= Offset) ? 0 : Opcodes[Offset];`

https://github.com/llvm/llvm-project/pull/73317
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