On 3/13/25 13:09, ben via cctalk wrote:
On 2025-03-13 10:47 a.m., Holm Tiffe via cctalk wrote:
Of course, now this could all be built on a few FPGAs,
and get vastly higher
performance.
Most designs seem to 8 bitter's, and all memory fits in
block ram.
Once you hit external ram/rom things slow down again.
That's the point where the fun ends..at least for me.
Yes, I've done
some designs on Altera CPLDs (schematic entry only),
bought a book about
Verilog and one about VHDL .. but spare time is low...
ADHL is a nice way to program CPLD's and FPGA's.
I tried using Altera fpga's, but routing never worked
reliable for me.
Since every brand of FPGA is just a little different, I
never could port stuff using Verlog or VHDL.
WinCUPL is what I use to program CPLD's (Amtel) now.
I use Xilinx parts pretty exclusively. Generally, pure VHDL
files can be ported to their XC9500 or coolrunner II family
of CPLDs, or their Spartan FPGAs with minimal issues. If
you use some of their design blocks then that ties you to a
particular family.
For building stuff, your choice of crystal oscillators is
really limited
so you are stuck with common speeds. Making it fast might
not be possible if your timing is off by a few nS and you
have to pick the next
slower sized oscillator.
The Xilinx FPGAs have a "clock manager" that allows you to
configure PLL clock multiplication of whatever external
clock you supply.
Jon
